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| TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CM22FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". TMP92CM22 CMOS 32-Bit Microcontrollers TMP92CM22FG 1. Outline and Device Characteristics TMP92CM22 is high-speed advanced 32-bit microcontroller developed for controlling equipment, which processes mass data. TMP92CM22FG is a microcontroller, which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92CM22F is housed in a 100-pin flat package. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H1 CPU) * * * * Compatible with TLCS-900, 900/L, 900/L1, 900/H, and 900/H2's instruction code 16 Mbytes of linear address space General-purpose register and register banks Micro DMA: 8 channels (250 ns/4 bytes at fSYS = 20 MHz, best case) (2) Minimum instruction execution time: 50 ns (at fSYS = 20 MHz) (3) Internal memory * * Internal RAM: 32 Kbytes (32-bit 1-clock access, programmable) Internal ROM: None 070208EBP RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 021023_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S 92CM22-1 2007-02-16 TMP92CM22 (4) External memory expansion * * * * Expandable up to 16 Mbytes (Shared program/data area) Can simultaneously support 8-/16-bit width external data bus Dynamic data bus sizing Separate bus system Chip select output: 4 channels (5) Memory controller (6) 8-bit timers: 4 channels (7) 16-bit timers: 2 channels (8) General-purpose serial interface: 2 channels * * * * UART/synchronous mode IrDA I2C bus mode Clock synchronous mode (9) Serial bus interface: 1 channel (10) 10-bit AD converter: 8 channels (11) Watchdog timer (12) Interrupts: 41 interrupts * * * 9 CPU interrupts: Software interrupt instruction and illegal instruction 25 internal interrupts: Seven selectable priority levels 7 external interrupts: Seven selectable priority levels (INT0 to INT5 and NMI ) (INT0 to INT3 selectable edge or level interrupt) RD (13) Input/output ports: 50 pins (exclude Data bus 8-bit, Address bus 24-bit and (14) Standby function * * * * * Three HALT modes: IDLE2 (Programmable), IDLE1, STOP PLL: fc = fOSCH x 4 (fc = 40 MHz at fOSCH = 10 MHz) Clock gear function: Select a high-frequency clock fc to fc/16 DVCC = 3.0 V to 3.6 V (fc max = 40 MHz) 100-pin QFP: P-LQFP100-1414-0.50F (15) Dual-clock controller pin) (16) Operating voltage (17) Package 92CM22-2 2007-02-16 TMP92CM22 PG0 to PG7 (AN0 to AN7) PG3 ( ADTRG ) AVCC AVSS VREFH VREFL PF0 (TXD0) PF1 (RXD0) PF2 (SCLK0/ CTS0 ) PF3 (TXD1) PF4 (RXD1) PF5 (SCLK1/ CTS1 ) PF6 to PF7 P90 (SCK) P91 (SO/SDA) P92 (SI/SCL) 10-bit 8-ch AD converter XWA XBC Serial I/O SIO0 XDE XHL XIX Serial I/O SIO1 XIY XIZ Port F Serial bus I/F SBI0 XSP 32 bits SR PC F 900/H1 CPU PLL W B D H IX IY IZ SP Data bus Port 1 Port 4 Port 5 PC0 (TA0IN) PC1 (TA1OUT/INT1) 8-bit timer (Timer A0) 8-bit timer (Timer A1) 8-bit timer (Timer A2) PC5 (TA3OUT/INT2) 8-bit timer (Timer A3) 32-Kbyte RAM PC6 (TB00UT0/INT3) PD0 (TB1IN0/INT4) PD1 (TB1IN1/INT5) PD2 (TB1OUT0) PD3 (TB1OUT1) 16-bit timer (Timer B1) Port A 16-bit timer (Timer B0) Watchdog timer Port 6 A C E L Mode controller Interrupt controller H-OSC Clock gear DVCC [3] DVSS [4] X1 X2 RESET AM0 AM1 NMI PC3(INT0) D0 to D7 P10 to P17 (D8 to D15) P40 to P47 (A0 to A7) P50 to P57 (A8 to A15) P60 to P67 (A16 to A23) P70 ( RD ) P71 ( WRLL ) P72 ( WRLU ) P73 P74 (CLKOUT) P75 (R/ W ) P76 ( WAIT ) P80 ( CS0 ) Port 7 Port 8 P81 ( CS1 ) P82 ( CS2 ) P83 ( CS3 ) PA0 to PA2 PA7 Figure 1.1 TMP92CM22 Block Diagram 92CM22-3 2007-02-16 TMP92CM22 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CM22FG, their names and functions are as follows. 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment of the TMP92CM22FG. PD1/TB1IN1/INT5 PD0/TB1IN0/INT4 PD3/TB1OUT1 PD2/TB1OUT0 P91/SO/SDA P92/SI/SCL P74/CLKOUT P72/WRLU P75/R/W P71/WRLL P76/WAIT P90/SCK 100 95 90 85 80 P67/A23 P83/CS3 P82/CS2 P81/CS1 P80/CS0 PA2 PA1 PA0 P70/RD DVSS4 AVCC AVSS P73 VREFL VREFH PG0/AN0 PG1/AN1 PG2/AN2 PG3/AN3/ ADTRG PG4/AN4 PG5/AN5 PG6/AN6 PG7/AN7 PA7 PC0/TA0IN PC1/TA1OUT/INT1 PC5/TA3OUT/INT2 PC6/TB0OUT0/INT3 PF0/TXD0 PF1/RXD0 PF2/SCLK0/ CTS0 PF3/TXD1 PF4/RXD1 PF5/SCLK1/ CTS1 PF6 PF7 NMI 1 75 P66/A22 P65/A21 P64/A20 DVCC3 5 70 P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 10 TMP92CM22 QFP100 Top view P56/A14 65 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 60 P50/A8 P47/A7 P46/A6 P45/A5 15 20 55 P44/A4 P43/A3 P42/A2 P41/A1 P40/A0 DVCC1 25 30 35 40 45 50 DVSS3 P10/D8 P11/D9 RESET D0 D1 D2 D3 D4 D5 D6 AM1 AM0 D7 X1 X2 P12/D10 P13/D11 P14/D12 P15/D13 P16/D14 Figure 2.1.1 Pin Assignment Diagram (100-Pin QFP) PC3/INT0 P17/D15 DVSS2 DVCC2 DVSS1 92CM22-4 2007-02-16 TMP92CM22 2.2 Pin Names and Functions The following tables show the names and functions of the input/output pins. Table 2.2.1 Pin Names and Functions (1/2) Pin Names D0 to D7 P10 to P17 Number of Pins 8 8 I/O I/O I/O I/O Data (Lower): Data bus D0 to D7. Functions Port 1: I/O port that allows I/O to be selected at the bit level. (when used to the external 8-bit bus.) Data: Data bus D8 to D15. Port 4: I/O port. Address: Address bus A0 to A7. Port 5: I/O port. Address: Address bus A8 to A15. Port 6: I/O port. Address: Address bus A16 to A23. Port 70: Output port. Read: Strobe signal for reading external memory. Port 71: Output port. Write: Strobe signal for writing data to pins D0 to D7. Port 72: Output port. Write: Strobe signal for writing data to pins D8 to D15. Port 73: Output port. Port 74: Output port. Clock: Output system clock. Port 75: Output port. Read/write: This port is 1 when read and dummy cycle. This port is 0 when write cycle. Port 76: I/O port. Wait: Pin used to request bus wait to CPU. Port 80: Output port. Chip select 0: Outputs 0 when address is within specified address area. Port 81: Output port. Chip select 1: Outputs 0 when address is within specified address area. Port 82: Output port. Chip select 2: Outputs 0 when address is within specified address area. Port 83: Output port. Chip select 3: Outputs 0 when address is within specified address area. Port 90: I/O port. Serial bus interface clock I/O data at SIO mode. Port 91: I/O port. Serial bus interface send data at SIO mode. Serial bus interface send/receive data at I C mode. (Open-drain output mode by programmable.) Port 92: I/O port. Serial bus interface receive data at SIO mode. Serial bus interface clock I/O data at I C mode. (Open-drain output mode by programmable.) 2 2 D8 to D15 P40 to P47 A0 to A7 P50 to P57 A8 to A15 P60 to P67 A16 to A23 P70 RD 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 I/O Output I/O Output I/O Output Output Output Output Output Output Output Output Output Output Output Output I/O Input Output Output Output Output Output Output Output Output I/O I/O I/O Output I/O I/O P71 WRLL P72 WRLU P73 P74 CLKOUT P75 R/ W P76 WAIT P80 CS0 P81 CS1 P82 CS2 P83 CS3 P90 SCK P91 SO SDA P92 SI SCL PA0 to PA2, PA7 1 1 Input I/O 4 Input Port A0 to A2, A7: Input port (with pull-up resistor). 92CM22-5 2007-02-16 TMP92CM22 Table 2.2.2 Pin Names and Functions (2/2) Pin Names PC0 TA0IN PC1 INT1 TA1OUT PC3 INT0 PC5 INT2 TA3OUT PC6 INT3 TB0OUT0 PD0 INT4 TB1IN0 PD1 INT5 TB1IN1 PD2 TB1OUT0 PD3 TB1OUT1 PF0 TXD0 PF1 RXD0 PF2 SCLK0 CTS0 Number of Pins 1 I/O I/O Input I/O Input Output I/O Input I/O Input Output I/O Port C0: I/O port. Timer input: 8-bit timer A0 input. Port C1: I/O port. Functions 1 Interrupt request pin 1: Interrupt request pin with programmable level/rising edge/falling edge. Timer output: 8-bit timer A0 or timer A1 output. Port C3: I/O port. Interrupt request pin 0: Interrupt request pin with programmable level/rising edge/falling edge. Port C5: I/O port. Interrupt request pin 2: Interrupt request pin with programmable level/rising edge/falling edge. Timer output: 8-bit timer A2 or timer A3 output. Port C6: I/O port. Interrupt request pin 3: Interrupt request pin with programmable level/rising edge/falling edge. Timer output: 16-bit timer B0 output. Port D0: I/O port. Interrupt request pin 4: Interrupt request pin with programmable rising edge/falling edge. Timer input: 16-bit timer B1 input 0. Port D1: I/O port. Interrupt request pin 5: Interrupt request pin with programmable rising edge/falling edge. Timer input: 16-bit timer B1 input 1. Port D2: I/O port. Timer output: 16-bit timer B1 output 0. Port D3: I/O port. Timer output: 16-bit timer B1 output 1. Port F0: I/O port. Serial send data 0: (Open-drain output mode by programmable.) Port F1: I/O port. Serial receive data 0. Port F2: I/O port. Serial 0 clock I/O. Serial data send enable 0 (Clear to send). Port F3: I/O port. Serial send data 1: (Open-drain output mode by programmable.) Port F4: I/O port. Serial receive data 1. Port F5: I/O port. Serial 1 clock I/O. Serial data send enable 1 (Clear to send). Port F6 to F7: I/O port. Port G0 to G7: Input port. Analog input 0 to 7: Pin used to input to AD converter. AD trigger: Pin used to request AD converter start (Share with PG3). Non-Maskable interrupt request pin. Operation mode: Fixed to AM1 = "0", AM0 = "1": External 16-bit bus start, 8-/16-bit dynamic sizing. Fixed to AM1 = "1", AM0 = "0": External 8-bit bus start, 8-/16-bit dynamic sizing. High-frequency oscillator connection pin. Reset: Initialize TMP92CM22 (Schmitt input, with pull-up resistor). Pin for reference voltage input to AD converter (H). Pin for reference voltage input to AD converter (L). Power supply pin for AD converter. GND pin for AD converter (0 V). Power supply pins (All Vcc pins should be connected with the power supply pin). 1 1 1 Input Output I/O 1 Input Input I/O 1 Input Input I/O Output I/O Output I/O Output I/O Input I/O I/O Input I/O Output I/O Input I/O I/O Input I/O Input Input Input Input Input I/O Input Input Input 1 1 1 1 1 PF3 TXD1 PF4 RXD1 PF5 SCLK1 CTS1 1 1 1 2 8 1 2 2 1 1 1 1 1 3 4 PF6 to PF7 PG0 to PG7 AN0 to AN7 ADTRG NMI AM0, AM1 X1/X2 RESET VREFH VREFL AVCC AVSS DVCC DVSS - GND pins (0 V) (All DVSS pins should be connected with GND (0 V)). 92CM22-6 2007-02-16 TMP92CM22 3. Operation This section describes the basic components, functions and operation of the TMP92CM22. 3.1 CPU The TMP92CM22 incorporates a high-performance 32-bit CPU (The TLCS-900/H1 CPU). For a description of this CPU's operation, please refer to the section of this data book which describes the TLCS-900/H1 CPU. The following sub-sections describe functions peculiar to the CPU used in the TMP92CM22; these functions are not covered in the section devoted to the TLCS-900/H1 CPU. 3.1.1 Outline "TLCS-900/H1 CPU" is high-speed and high-performance CPU based on "TLCS-900/L1 CPU". "TLCS-900/H1 CPU" has expanded 32-bit internal and external data bus to process instructions more quickly. Outline of "TLCS-900/H1" CPU are as follows: Table 3.1.1 Outline of CPU Width of CPU address bus Width of CPU data bus Internal operating frequency Minimum bus cycle Function of data bus sizing Internal RAM Internal I/O External device Minimum instruction execution cycle Conditional jump Instruction queue buffer Instruction set 24 bits 32 bits 20 MHz 1-clock access (50 ns at 20 MHz) 8 bits 32 bits 1-clock access 8-/16-bit 8-/16-bit 8 bits 2-clock access (can insert some waits) 1 clock (50 ns at 20 MHz) 2 clocks (100 ns at 20 MHz) 12 bytes Compatible with TLCS-900, 900/L, 900/H, 900/L1, and 900/H2 instruction codes (However, NORMAL, MAX, MIN, and LDX instructions is deleted) Only maximum mode 8 channels 2-clock access 5-to 6-clock access 900/H1 I/O 900/H1 I/O CPU mode Micro DMA 92CM22-7 2007-02-16 TMP92CM22 3.1.2 Reset Operation When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low for at least 20 system clocks (16 s at fc = 40 MHz). When the reset has been accepted, the CPU performs the following: * Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<7:0> Data in location FFFF00H PC<15:8> Data in location FFFF01H PC<23:16> Data in location FFFF02H * * * Sets the stack pointer (XSP) to 00000000H. Sets bits When the reset is released, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. * * Initializes the internal I/O registers as "Table of Special Function Registers (SFRs)" in Section 5. Sets the input or output port to general-purpose input port. Internal reset is released as soon as external reset is released and RESET input pin is set to "H". The operation of memory controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on the TMP92CM22 may be spoiled because the control signals are unstable until power supply becomes stable after power on reset. Figure 3.1.1 shows the timing of a reset for the TMP92CM22. 92CM22-8 2007-02-16 TMP92CM22 VCC 3.3 V RESET Oscillator operation time + 20 system clocks 0 [s] (Min) Figure 3.1.1 Reset Timing Example 3.1.3 Outline of Operation Mode Set AM1 and AM0 pins to "10" to use 8-bit external bus, or set it to "01" to use 16-bit external bus. Table 3.1.2 Operation Mode Setup Table Operation 16-bit external bus start 8-/16-bit dynamic bus sizing 8-bit external bus start 8-/16-bit dynamic bus sizing Mode Setting Input Pin RESET AM1 0 1 AM0 1 0 92CM22-9 2007-02-16 TMP92CM22 3.2 Memory Map Figure 3.2.1 shows memory map of TMP92CM22. 000000H Internal I/O (8 Kbytes) 000100H 001FE0H 002000H Internal RAM (32 Kbytes) Direct area(n) 64-Kbyte area (nn) 00A000H 010000H External memory F00000H F10000H Provisinal emulator control area (64 Kbytes) External memory 16-Mbyte area (R) ( - R) (R + ) (R + R8/16) (R + d8/16) (nnn) FFFF00H Vector table (256 bytes) FFFFFFH ( = Internal area) Figure 3.2.1 Memory Map Note 1: When use emulator, optional 64 Kbytes of 16-Mbyte area are used to control emulator. Therefore, don't use this area. Note 2: Don't use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved. Note 3: On emulator WRLL signal, WRLU signal and emulator control area is accessed. Be careful to use extend memory. RD signal are asserted, when provisional 92CM22-10 2007-02-16 TMP92CM22 3.3 Clock Function and Standby Function TMP92CM22 contains (1) Clock gear, (2) Standby controller and (3) Noise-reducing circuit. It is used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 SFRs 3.3.3 System Clock Controller 3.3.4 Clock Doubler (PLL) 3.3.5 Noise Reduction Circuits 3.3.6 Standby Controller 92CM22-11 2007-02-16 TMP92CM22 The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2 pins and PLL). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) Release reset IDLE2 mode (I/O operation) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stop all circuit ) Single clock mode transition figure Reset (fOSCH/32) IDLE2 mode (I/O operation) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operation) IDLE1 mode (Operate oscillator and PLL ) Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stop all circuit ) Instruction Instruction Interrupt Instruction Interrupt NORMAL mode (4 x fOSCH/gear value/2) (Using PLL) (b) Dual clock mode transition figure Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency selected by SYSCR1 92CM22-12 2007-02-16 TMP92CM22 3.3.1 Block Diagram of System Clock SYSCR2 fSYS fiO T0 TMRA0 to TMRA3 and TMRB0 to TMRB1 Prescaler CPU RAM Interrupt controller SIO0 and SIO1 Prescaler ADC I/O port SBI T Prescaler WDT Figure 3.3.2 Block Diagram of Dual Clock and System Clock 92CM22-13 2007-02-16 TMP92CM22 3.3.2 SFRs 7 SYSCR0 (10E0H) Bit symbol Read/Write After reset Function SYSCR1 (10E1H) Bit symbol Read/Write After reset Function - R/W 1 Always write "1". 6 5 4 3 2 - R/W 0 Always write "0". 1 0 - 0 Always write "0". GEAR2 R/W 1 GEAR1 0 GEAR0 0 Select gear value of highfrequency oscillator 000: High-frequency oscillator 001: High-frequency oscillator/2 010: High-frequency oscillator/4 011: High-frequency oscillator/8 100: High-frequency oscillator/16 101: 110: 111: Reserved SELDRV 0 SYSCR2 (10E2H) Bit symbol Read/Write After reset Function - R/W 0 Always write "0". WUPTM1 1 WUPTM0 0 HALTM1 1 00: Reserved HALTM0 1 R/W Select WUP time for oscillator 00: Reserved 01: 2 /Input frequency 10: 2 /Input frequency 11: 2 /Input frequency 16 14 8 Select HALT mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode Note: The unassigned register, SYSCR0 Figure 3.3.3 SFR for System Clock 92CM22-14 2007-02-16 TMP92CM22 7 PLLCR (10E8H) Bit symbol Read/Write After reset Function 0 0: PLL stop 1: PLL run PLLON R/W 6 FCSEL 0 0: fc = OSCH 1: fc = PLL (x 4) 5 LWUPFG R 0 PLL warm-up flag 0: Don't end up or stop 1: End up 4 3 2 1 0 Note: Logic of PLLCR Figure 3.3.4 SFR for PLL 7 EMCCR0 (10E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect 0: OFF 1: ON EMCCR1 (10E4H) Bit symbol Read/Write After reset Function EMCCR2 (10E5H) Bit symbol Read/Write After reset Function 6 5 4 3 2 EXTIN 0 1 DRVOSCH R/W 1 0 - 1 1: fc fc oscillator Always external driver ability write "1". clock 1: Normal 0: Weak Switching the protect ON/OFF by write to following 1st-KEY, 2nd-KEY 1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write Note: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set EMCCR0 Figure 3.3.5 SFR for Noise 92CM22-15 2007-02-16 TMP92CM22 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It is used as input that fc outputted from high-frequency oscillation circuit and PLL (Clock doubler) SYSCR1 Example: Changing to a high-frequency gear SYSCR1 X: Don't care EQU LD 10E1H (SYSCR1), XXXX0100B ; Changes system clock fSYS to fc/32. (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 Example: SYSCR1 EQU LD LD 10E1H (SYSCR1), XXXX0001B (DUMMY), 00H Instruction to be executed after clock gear has changed. ; ; Changes fSYS to fc/4. Dummy instruction. 92CM22-16 2007-02-16 TMP92CM22 3.3.4 Clock Doubler (PLL) PLL outputs the fPLL clock signal, which is four times as fast as fOSCH. A reset initializes PLL to stop status, setting to PLLCR register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lockup time. Note 1: Input frequency limitation for PLL The limitation of input frequency (High-frequency oscillation) for PLL is the following. fOSCH = 4 to 10 MHz (Vcc = 3.0 V to 3.6 V) Note 2: PLLCR Example 1: PLL starting PLLCR EQU LD LUP: BIT JR LD X: Don't care 10E8H (PLLCR), 10XXXXXXXB 5, (PLLCR) Z, LUP (PLLCR), 11XXXXXXB ; ; ; ; Enables PLL operation and starts lockup. Detects end of lockup. Changes fc from 10 MHz to 40 MHz. 92CM22-17 2007-02-16 TMP92CM22 Example 2: PLL stopping PLLCR EQU LD LD X: Don't care Limitation point on the use of PLL 1. When PLL is started, don't set fc from fOSCH to fPLL at same time. Don't setting: LD LD (PLLCR), 00H (PLLCR), C0H 2. When PLL is started, don't set fc from fOSCH to fPLL at same time. Don't setting: LD LD (PLLCR), C0H (PLLCR), 00H 92CM22-18 2007-02-16 TMP92CM22 3.3.5 Noise Reduction Circuits Noise reduction circuits are built in for reduction EMI (Unnecessary radius noise) and reinforcement EMS (Measure of endure noise), allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Single drive for high-frequency oscillator (3) SFR protection of register contents These functions need setting by EMCCR0 to EMCCR2. (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when connect oscillator to outside. (Block diagram) fOSCH C1 Oscillator EMCCR0 (Setting method) The drivability of the oscillator is reduced by writing "0" to EMCCR0 Note: When use drivability reduction function of oscillator, please use in case of fOSCH = 4 MHz to 10 MHz condition. 92CM22-19 2007-02-16 TMP92CM22 (2) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) fOSCH X1 pin Oscillation enable ( STOP + EMCCR0 < EXTIN > ) EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing "1" to EMCCR0 92CM22-20 2007-02-16 TMP92CM22 (3) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that is in the state which is fetch impossibility by stopping of clock, memory control register (Memory controller) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BEXCSL/H, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, and PMEMCR 2. Clock gear (EMCCR1, EMCCR2 write enable) SYSCR0, SYSCR1, SYSCR2, and EMCCR0 (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 registers. (Double key) 1st-KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2. 2nd-KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2. A state of protection can be confirmed by reading EMCCR0 92CM22-21 2007-02-16 TMP92CM22 3.3.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1, or STOP mode, depending on the contents of the SYSCR2 Table 3.3.1 SFR Seting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRB0 TMRB1 SIO0 SIO1 AD converter WDT SBI SFR TA01RUN b. c. IDLE1: Only internal oscillator operates. STOP: All internal circuit stop. The operation of each of the different HALT modes is described in Table 3.3.2. Table 3.3.2 Each Block Operation in HALT Mode HALT Mode SYSCR2 CPU Operation block I/O port TMRA, TMRB SIO, *SBI AD converter WDT IDLE2 11 Stop Keep the state when the HALT instruction is executed. * Selection enable operation block to programmable IDLE1 10 STOP 01 Refer Table 3.3.5, Table 3.3.6 Stop *: Except clocked-synchronous 8-bit SIO mode for SBI. 92CM22-22 2007-02-16 TMP92CM22 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register 92CM22-23 2007-02-16 TMP92CM22 Table 3.3.3 Source of Halt State Release and Halt Release Operation Status of Received Interrupt HALT Mode NMI Source of HALT state release INTWDT INT0 to 3 (Note1) Interrupt INT4 to 5 INTTA0 to 3, INTTB00, 01, 10, 11, O0, O1 INTRX0 to 1, TX0 to 1 INTAD INTSBE0 Reset Interrupt Enable (Interrupt level) (Interrupt mask) Programmable IDLE2 Interrupt Disable (Interrupt level) < (Interrupt mask) Programmable IDLE2 IDLE1 x x x x x x x STOP x *1 x x x x x x IDLE1 - - STOP - - - - x x x x x x x x x x x x *1 x x x x x x Initialize LSI : After release the HALT mode, CPU starts interrupt processing. After release the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. (Interrupt don't process.) It can not be used to release the HALT mode. The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. Release the HALT mode is executed after passing the warm-up time. : x: -: *1: Note 1: When the HALT mode is released by INT0 to INT3 interrupts of the level mode in the interrupt enabled status, hold this level until starting interrupt processing. Changing level before holding level, interrupt processing is correctly started. Note 2: When use external interrupt INT4 to INT5 are used during IDLE2 mode, set 16-bit timer RUN register TB1RUN Address 8203H 8206H 8209H 820BH 820EH INT0 LD LD EI LD HALT (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; ; ; ; ; Selects INT0 interrupt rising edge. Sets INT0 interrupt level to 6. Sets CPU interrupt level to 5. Sets HALT mode to IDLE1 mode. Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 92CM22-24 2007-02-16 TMP92CM22 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt of releasing halt IDLE2 mode Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Released by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator operates. The system clock stops. And, pin state in IDLE1 mode depend on setting SYSCR2 X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt of releasing halt IDLE1 mode Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Released by Interrupt 92CM22-25 2007-02-16 TMP92CM22 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 Warm-up time X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt of releasing halt STOP mode Figure 3.3.8 Timing Chart for STOP Mode Halt State Released by Interrupt Table 3.3.4 Sample Warm-up Times after Rrelease of STOP Mode at fOSCH = 10 MHz SYSCR2 25.6 s 8 10 (214) 1.638 ms 11 (216) 6.554 ms 92CM22-26 2007-02-16 TMP92CM22 Table 3.3.5 Input Buffer State Table Input Buffer State Port Name Input Function Name Input Buffer State During Reset When Used as function Pin ON upon external read - Input Buffer State When Used as function Pin OFF When Used as Input Port - When Used as Input Port - In HALT mode (IDLE1/STOP) Condition A (Note) Condition B (Note) When When When When Used as Used as Used as Used as function Input function Input Pin Port Pin Port - - D0-D7 P10-P17 P40-P47 P50-P57 P60-P67 P76 P90 P91 P92 PA0-PA7(*1) PC0 PC1 PC3 PC5 PC6 PD0 PD1 PD2 PD3 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0-2, PG4-7(*2) PG3(*2) D0-D7 D8-D15 OFF OFF - - - WAIT SCK SDA SI SCL OFF - - - OFF OFF ON OFF OFF OFF ON - OFF - TA0IN INT1 INT0 INT2 INT3 INT4, TB1IN0 INT5, TB1IN1 - ON OFF ON - OFF ON OFF ON - OFF ON OFF ON ON ON ON ON ON ON OFF OFF OFF - - - RXD0 SCLK0, CTS0 - - - - ON - ON - ON OFF OFF - OFF OFF - OFF - RXD1 SCLK1, CTS1 ON ON ON OFF OFF - - - - OFF ADTRG ON upon port read - - - - OFF NMI RESET(*1) AM0,1 X1 - - - ON ON ON - ON - ON - ON: The buffer is always turned on. A current flows the input buffer if the input pin is not driven. OFF: The buffer is always turned off. -: No applicable *1: Port having a pull-up/pull-down resistor. *2: AIN input does not cause a current to flow through the buffer. Note: Condition A/B are as follows. SYSCR2 register setting 92CM22-27 2007-02-16 TMP92CM22 Table 3.3.6 Output Buffer State Table Output Buffer State Port Name Output Function Name When the CPU is Operating During Reset When Used as Function Pin ON upon external read When Used as Output Port - In HALT mode(IDLE2) When Used as Function Pin OFF When Used as Output Port - In HALT mode (IDLE1/STOP) Condition A (Note) When Used as Function Pin When Used as Output Port - Condition B (Note) When Used as Function Pin OFF When Used as Output Port - D0-D7 P10-P17 P40-P47 P50-P57 P60-P67 P70 P71 P72 P73 P74 P75 P76 P80 P81 P82 P83 P90 P91 P92 PC0 PC1 PC3 PC5 PC6 PD0 PD1 PD2 PD3 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 X2 D0-D7 D8-D15 A0-A7 A8-A15 A16-A23 RD OFF ON OFF ON ON ON ON WRLL WRLU WRUL WRUU R/W - OFF - - - - CS0 CS1 CS2 CS3 SCK SO SCL - - ON ON ON OFF ON ON - ON - ON OFF - TA1OUT - ON - ON - OFF - ON - TA3OUT TB0OUT - - ON - ON - OFF - ON - TB1OUT0 TB1OUT1 TXD0 - OFF ON ON ON - - - - OFF ON SCLK0 TXD1 - ON - ON - OFF - ON - SCLK1 - - - ON - - ON - OFF - - ON - ON IDLE1: ON, STOP: High level output ON: The buffer is always turned on. When the bus is released, however ,output buffers for some pins are turned off. OFF: The buffer is always turned off. -: No applicable Note: Condition A/B are as follows. SYSCR2 register setting HALT mode IDLE1 Condition B Condition A Condition B STOP Condition A Condition B 92CM22-28 2007-02-16 TMP92CM22 3.4 Interrupt Interrupts of TLCS-900/H1 are controlled by the CPU interrupt mask flip-flop (IFF2:0) and by the built-in interrupt controller. The TMP92CM22 has a total of 41 interrupts divided into the following types: Interrupts generated by CPU: 9 sources (Software interrupts: 8 sources, illegal instruction interrupt: 1 source) External interrupts ( NMI and INT0 to INT5): 7 sources Internal I/O interrupts: 17 sources High-speed DMA interrupts: 8 sources A individual interrupt vector number (Fixed) is assigned to each interrupt. One of six priority level (Variable) can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. If multiple interrupts is generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupts mask register 92CM22-29 2007-02-16 TMP92CM22 Interrupt processing Interrupt specified by micro DMA start vector? No Interrupt vector "V" read Interrupt request F/F clear General-purpose interrupt processing PUSH PC PUSH SR SR Yes Micro DMA soft start request Clear interrupt request flag Data transfer by micro DMA Micro DMA processing COUNT COUNT - 1 COUNT = 0 No Yes Generating INTTC interrupt clear micro DMA start vector PC(FFFF00H) + V) Interrupt process program RETI instruction POP SR POP PC INTNEST INTNEST-1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 92CM22-30 2007-02-16 TMP92CM22 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L, TLCS-900/H, and TLCS-900/L1. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: The smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register 92CM22-31 2007-02-16 TMP92CM22 Table 3.4.1 TMP92CM22 Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Maskable Nonmaskable Type Interrupt Source Reset or "SWI0" instruction "SWI1" instruction "Illegal instruction" or "SWI2" instruction "SWI3" instruction "SWI4" instruction "SWI5" instruction "SWI6" instruction "SWI7" instruction NMI: External interrupt input pin INTWD: Watchdog Timer Micro DMA (Note 2) INT0: External interrupt input pin INT1: External interrupt input pin INT2: External interrupt input pin INT3: External interrupt input pin (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) INTP0: Protect 0 (WR to SFR) (Reserved) INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTB00: 16-bit timer 0 INTTB01: 16-bit timer 0 (Reserved) (Reserved) INTTBO0: 16-bit timer 0 (Overflow) (Reserved) INTRX0: Serial 0 (SIO0) receive INTTX0: Serial 0 (SIO0) transmission INTRX1: Serial 1 (SIO1) receive INTTX1: Serial 1 (SIO1) transmission (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) INT4: External interrupt input pin INT5: External interrupt input pin INTTB10: 16-bit timer 1 INTTB11: 16-bit timer 1 INTTBO1: 16-bit timer 1 (Overflow) (Reserved) INTSBE0: SBI I C bus transfer end (Channel 0) (Reserved) (Reserved) (Reserved) 2 Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H 00C8H Address Refer to Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H FFFFC8H Micro DMA Start Vector - 0AH (Note 1) 0BH (Note 1) 0CH (Note 1) 0DH (Note 1) 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H (Note 1) 21H 22H (Note 1) 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 92CM22-32 2007-02-16 TMP92CM22 Address Refer to Vector FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H FFFFE4H FFFFE8H FFFFECH FFFFF0H : FFFFFCH Default Priority 52 53 54 55 56 57 58 59 60 Type Interrupt Source INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) Vector Value 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H 00E4H 00E8H 00ECH 00F0H : 00FCH Micro DMA Start Vector 33H 34H 35H 36H 37H 38H 39H 3AH 3BH - Maskable INTTC4: Micro DMA end (Channel 4) INTTC5: Micro DMA end (Channel 5) INTTC6: Micro DMA end (Channel 6) INTTC7: Micro DMA end (Channel 7) (Reserved) Note 1 : When initiating initiating micro DMA, set at edge detect mode. Note 2 : Micro DMA default priority. Micro DMA initiation takes priority over other maskable interrupts 92CM22-33 2007-02-16 TMP92CM22 3.4.2 Micro DMA In addition to general-purpose interrupt processing, the TMP92CM22 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source. Because the micro DMA function is implemented through the CPU, when the CPU is placed in a stand-by state by a Halt instruction, the requirements of the micro DMA will be ignored (pending). Micro DMA is supports 8 channels and can be transferred continuously by specifying the micro DMA burst function as below. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The eight micro DMA channels allow micro DMA processing to be set for up to eight types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte, two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: the lower the channel number, the higher the priority (channel 0 thus has the highest priority and channel 7 the lowest). If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (i.e., interrupt requests should be disabled). If micro DMA and general purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. (Note) In this case, edge triggered interrupts are the only kinds of general interrupts which can be accepted. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in theFigure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 92CM22-34 2007-02-16 TMP92CM22 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: one-byte transfers, two-byte (one-word) transfer and four-byte transfer. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from memory to memory, from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.4.2 (1), detailed description of the transfer mode register. Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 34 different interrupts - the 33 interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer destination address INC mode (micro DMA transfers are the same in every mode except counter mode). (The conditions for this cycle are as follows: Both source and destination memory are internal RAM and multiples by 4 numbered source and destination addresses.) 1 state a. CLK A0 to A23 src dst b. c. d. e. Figure 3.4.2 Timing for Micro DMA Cycle States 1 to 2: Instruction fetches cycle (Gets next address code). If the instruction queue buffer is FULL , this cycle becomes a dummy cycle. State 3: State 4: State 5: Micro DMA read cycle. Micro DMA writes cycle. (The same as in state 1, 2.) 92CM22-35 2007-02-16 TMP92CM22 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP92CM22 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing "1" to each bit of DMAR register causes micro DMA once (If write "0" to each bit, micro DMA doesn't operate). At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to "0". Only one channel can be set for DMA request at once. (Do not write 1 to more than one bit.) When writing again 1 to the DMAR register, check whether the bit is 0 before writing 1. If read "1", micro DMA transfer isn't started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is "0" after start up of the micro DMA. If execatee soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writign to other bits by mistake. Symbol Name DMA request Address 109H (Prohibit RMW) 7 DREQ7 6 DREQ6 5 DREQ5 4 DREQ4 R/W 3 DREQ3 2 DREQ2 1 DREQ1 0 DREQ0 DMAR 0 0 0 0 0 0 0 0 1: DMA request in software (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. Data setting for these registers is done by an "LDC cr, r" instruction. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA Source address register 0: only use LSB 24 bits. DMA Destination address register 0: only use LSB 24 bits. DMA Counter register 0: 1 to 65536. DMA Mode register 0. Channel 7 DMAS7 DMAD7 DMAC7 DMAM7 8 bits 16 bits 32 bits DMA Source address register 7. DMA Destination address register 7. DMA Counter register 7. DMA Mode register 7. 92CM22-36 2007-02-16 TMP92CM22 (4) Detailed description of the transfer mode register 0 0 0 Mode DMAM0 to DMAM7 DMAM [4:0] 000 zz Destination address INC mode (DMADn +) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTC Source address DEC mode (DMADn -) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTC Source address INC mode (DMADn) (DMASn +) DMACn DMACn - 1 If DMACn = 0 then INTTC Source address DEC mode (DMADn) (DMASn -) DMACn DMACn - 1 If DMACn = 0 then INTTC Source address INC mode (DMADn +) (DMASn +) DMACn DMACn - 1 If DMACn = 0 then INTTC Source address DEC mode (DMADn -) (DMASn -) DMACn DMACn - 1 If DMACn = 0 then INTTC Destination address fixed mode (DMADn) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTC Counter mode DMASn DMASn + 1 DMACn DMACn - 1 If DMACn = 0 then INTTC Operation Execution Time 5 states 001 zz 5 states 010 zz 5 states 011 zz 5 states 100 zz 6 states 101 zz 6 states 110 zz 5 states 111 00 5 states ZZ : 00 = 1-byte transfer : 01 = 2-byte transfer : 10 = 4-byte transfer : 11 = (Reserved) Note 1: The execution state number shows number of best case (1-state memory access). 1 state = 50 ns (at internal 20 MHz) Note 2: "n" shows micro DMA channel number (0 to 7). 92CM22-37 2007-02-16 TMP92CM22 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 33 interrupts channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to 0 in the following cases: When reset occurs When the CPU reads the channel vector after accepted its interrupt When executing an instruction that clears the interrupt (Write DMA start vector to INTCLR register) When the CPU receives a micro DMA request When the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. If interrupt request with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value 92CM22-38 2007-02-16 Interrupt controller Interrupt request flag S Q 1 Interrupt request signal to CPU Priority encoder 1 3 3 Interuupt level detect Interrupt request signal 7 6 INTRQ2 to 0 IFF 2 to 0 then1 CPU (Reserved) Reset Interrupt vector read R IFF2:0 EI1 to 7 DI V = 20H V = 24H Decoder Y1 A Y2 Y3 B Y4 Y5 C Y6 6 Dn + 3 D1 36 D2 D3 Interrupt vector generator D4 D5 D6 Release halt Interrupt enable flag in CPU side Reset INTWD Priority setting register Dn Dn + 1 D Q Dn + 2 CLR Interrupt request flag S Q R INT0 Reset 1 2 A INTRQ2 to 0 3 Highest B 4 priority interrupt C 3 level select 5 6 (Highest priority is "7".) 7 D0 INT1 INT2 INT3 During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller Interrupt request F/F read Interrupt vector read Micro DMA acknowlege V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH 92CM22-39 D7 V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH Soft start 34 S Selector 0 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Micro DMA counter 0 interrupt INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 4 4-input OR Interrupt vector V read RESET INT0 to INT3 NMI Micro DMA start vector setting register Micro DMA request D 6 CLR INTTC0 Q If IFF = 7 then 0 A 1 2 3 D5 D4 D3 D2 D1 D0 2 B DMA0V DMA1V DMA2V DMA3V Micro DMA channel priority encoder 2 TMP92CM22 2007-02-16 Reset Micro DMA channel specification TMP92CM22 (1) Interrupt priority setting registers Symbol Name INT1&INT2 enable Address 7 I2C R 0 INT3 enable - - 0 - INTE3 D1H - - - Note: Always write "0". INTTA1 (TMRA1) INTETA01 INTTA0& INTTA1 enable D4H ITA1C R 0 INTTA2& INTTA3 enable ITA3C R 0 INTTB00& INTTB01 enable ITB01C R 0 INTTBO0 (Overflow) enable - R 0 - INTETBO0 DAH - - R/W Note: Always write "0". INTTX0 INTES0 INTRX0& INTTX0 enable DBH ITX0C R 0 INTRX1& INTTX1 enable ITX1C R 0 INT4& INT5 enable I5C R 0 INTTB10& INTTB11 enable ITB11C R 0 INTTBO1 (Overflow) enable - - - INTESB0 INTSBE0 enable E3H - - - INTEP0 INTP0 enable EEH - - - - - Note: Always write "0". - IP0C R 0 0 - - - Note: Always write "0". - ISBE0C R 0 0 INTP0 IP0M2 IP0M1 R/W 0 0 IP0M0 0 - INTETBO1 E2H - - - Note: Always write "0". - ITBO1C R 0 0 INTSBE0 ISBE0M2 ISBE0M1 R/W 0 0 ISBE0M0 0 ITB11M2 0 INT5 INTE45 E0H I5M2 I5M1 R/W 0 ITB11M1 R/W 0 0 0 ITB11M0 INTTB11 (TMRB1) INTETB1 E1H ITB10C R 0 0 I5M0 I4C R 0 0 ITB10M2 I4M2 0 INTTX1 INTES1 DCH ITX1M2 ITX1M1 R/W 0 0 ITX1M0 IRX1C R 0 0 INT4 I4M1 R/W 0 ITB10M1 R/W 0 0 INTTBO1 (TMRB1) ITBO1M2 ITBO1M1 ITBO1M0 R/W 0 0 0 ITB10M0 INTTB10 (TMRB1) I4M0 ITX0M2 ITX0M1 R/W 0 0 ITX0M0 IRX0C R 0 0 INTRX1 IRX1M2 IRX1M1 R/W 0 0 IRX1M0 - ITBO0C R 0 0 INTRX0 IRX0M2 IRX0M1 R/W 0 0 IRX0M0 0 ITB01M2 0 ITA3M2 ITA1M2 ITA1M1 R/W 0 ITA3M1 R/W 0 ITB01M1 R/W 0 0 0 ITB01M0 INTTB01 (TMRB0) INTETB0 D8H ITB00C R 0 0 0 ITA3M0 INTAT3 (TMRA3) D5H ITA2C R 0 0 ITB00M2 ITA1M0 ITA0C R 0 0 ITA2M2 - I3C R 0 0 ITA0M2 I3M2 6 INT2 INTE12 D0H I2M2 I2M1 R/W 0 0 I2M0 I1C R 0 0 INT3 I3M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITB00M1 R/W 0 0 INTTBO0 (TMRB0) ITBO0M2 ITBO0M1 ITBO0M0 R/W 0 0 0 ITB00M0 INTTB00 (TMRB0) 0 ITA2M0 INTAT2 (TMRA2) 0 ITA0M0 INTTA0 (TMRA0) I3M0 I1M2 5 4 3 2 INT1 I1M1 R/W 0 0 I1M0 1 0 INTETA23 92CM22-40 2007-02-16 TMP92CM22 Symbol Name INT0&INTAD enable Address 7 IADC R 0 6 INTAD IADM2 0 ITC1M2 0 ITC3M2 0 ITC5M2 0 ITC7M2 0 - - 5 IADM1 R/W 0 ITC1M1 R/W 0 ITC3M1 R/W 0 ITC5M1 R/W 0 ITC7M1 R/W 0 - - 4 IADM0 0 ITC1M0 0 ITC3M0 0 ITC5M0 0 ITC7M0 0 - 3 I0C R 0 ITC0C R 0 ITC2C R 0 ITC4C R 0 ITC6C R 0 ITCWD R 0 2 INT0 I0M2 0 ITC0M2 0 ITC2M2 0 ITC4M2 0 ITC6M2 0 INTWD - - 1 I0M1 R/W 0 ITC0M1 R/W 0 ITC2M1 R/W 0 ITC4M1 R/W 0 ITC6M1 R/W 0 - - - 0 I0M0 0 ITC0M0 0 ITC2M0 0 ITC4M0 0 ITC6M0 0 - - INTE0AD F0H INTTC1 (DMA1) INTETC01 INTTC0& INTTC1 enable F1H ITC1C R 0 INTTC2& INTTC3 enable ITC3C R 0 INTTC4& INTTC5 enable ITC5C R 0 INTTC6& INTTC7 enable ITC7C R 0 INTWD enable - - INTTC0 (DMA0) INTTC3 (DMA3) INTETC23 F2H INTTC2 (DMA2) INTTC5 (DMA5) INTETC45 F3H INTTC4 (DMA4) INTTC7 (DMA7) INTETC67 F4H INTTC6 (DMA6) INTWDT F7H Note: Always write "0". Interrupt request flag IxxM2 0 0 0 0 1 1 1 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt request. Sets interrupt priority level to 1. Sets interrupt priority level to 2. Sets interrupt priority level to 3. Sets interrupt priority level to 4. Sets interrupt priority level to 5. Sets interrupt priority level to 6. Disables interrupt request. 92CM22-41 2007-02-16 TMP92CM22 (2) External interrupt control Symbol Name Address 7 6 5 I3EDGE 0 IIMC Interrupt input mode control 00F6H (Prohibit RMW) 4 I2EDGE W 0 0 0 0 INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 0: Rising/ 0: Rising/ 0: Rising/ 0: Rising/ 0: Edge high high high high 1: Level 1: Falling/ 1: Falling/ 1: Falling/ 1: Falling/ low low low low 3 I1EDGE 2 I0EDGE 1 I0LE R/W 0 NMI 0: Falling edge 1: Falling and rising edges 0 NMIREE I3LE Interrupt input mode control2 00FAH (Prohibit RMW) 0 INT3 0: Edge 1: Level I2LE W 0 INT2 0: Edge 1: Level I1LE 0 INT1 0: Edge 1: Level IIMC2 H level L level Level edge Rising Falling Detect edge IxEDGE IxLE Note 1: Disable INT0 to INT3 before changing INT0 to 3 pins mode from "level" to "edge". Setting example for case of INT0: DI LD (IIMC) ,XXXXXX0-B LD (INTCLR),0AH NOP NOP NOP EI X: Don't care, -: No change ; ; ; Change from "level" to "edge". Clear interrupt request flag. Wait EI execution. Note 2: Note 3: See electrical characteristics in section 4 for external interrupt input pulse width. When release halt by INT0 to INT3 interrupt of level-mode in interrupt request enable, keep setting level by Example: Case of set "H" level interrupt ( 92CM22-42 2007-02-16 TMP92CM22 Table 3.4.2 Function Setting of External Interrupt Pin Interrupt Pin Shared Pin Mode Rising edge INT0 PC3 Falling edge High level Low level Rising edge INT1 PC1 Falling edge High level Low level Rising edge INT2 PC5 Falling edge High level Low level Rising edge INT3 PC6 Falling edge High level Low level INT4 INT5 PD0 PD1 Rising edge Falling edge Rising edge Setting Method IIMC 92CM22-43 2007-02-16 TMP92CM22 (3) SIO receive interrupt control Symbol Name SIO SIMC Interrupt mode control Address 7 6 5 4 3 2 1 IR1LE W 0 IR0LE 1 0: INTRX0 edge mode 1: INTRX0 level mode F5H (Prohibit RMW) 1 0: INTRX1 edge mode 1: INTRX1 level mode *INTRX1 level enables 0 1 Detect edge INTRX1 "H" level INTRX1 *INTRX0 rising edge enable 0 1 Detect edge INTRX0 "H" Level INTRX0 92CM22-44 2007-02-16 TMP92CM22 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH Clears interrupt request flag INT0 Symbol Name Interrupt clear control Address F8H (Prohibit RMW) 7 6 5 CLRV5 4 CLRV4 0 3 CLRV3 W 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 INTCLR 0 Interrupt clear (5) Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches "0", the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is completed. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number (Micro DMA chaining). 92CM22-45 2007-02-16 TMP92CM22 Symbol Name DMA0 Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 DMA4V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 DMA4V3 0 R/W 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 DMA4V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 DMA4V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA4V0 0 DMA0V start vector 100H 0 DMA1V5 DMA0 start vector DMA1 DMA1V start vector 101H R/W 0 DMA2V5 102H 0 DMA3V5 103H 0 DMA4V5 DMA4 DMA4V start vector 104H 0 DMA1 start vector DMA2 DMA2V start vector R/W DMA2 start vector DMA3 DMA3V start vector R/W DMA3 start vector R/W DMA4 start vector DMA5V5 DMA5 DMA5V start vector 105H 0 0 0 DMA5V4 DMA5V3 DMA5V2 0 DMA5V1 0 DMA5V0 0 R/W DMA5 start vector DMA6V5 DMA6 DMA6V start vector 106H 0 0 0 DMA6V4 DMA6V3 DMA6V2 0 DMA6V1 0 DMA6V0 0 R/W DMA6 start vector DMA7V5 DMA7V4 0 DMA7V3 0 DMA7V2 0 DMA7V1 0 DMA7V0 0 DMA7 DMA7V start vector 107H 0 R/W DMA7 start vector 92CM22-46 2007-02-16 TMP92CM22 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches 0. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name Address 7 DBST7 DMAB DMA burst 108H 0 6 DBST6 0 5 DBST5 0 4 DBST4 R/W 0 3 DBST3 0 2 DBST2 0 1 DBST1 0 0 DBST0 0 1: DMA request on burst mode 92CM22-47 2007-02-16 TMP92CM22 (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid this, an instruction which clears an interrupt request flag should always be placed after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 3-instructions (e.g., "NOP"x 3 times). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. Thus, when be changed interrupt request level to "0", change it after cleared corresponding interrupt request by INTCLR instruction. In the case of changing the value of the interrupt mask register In level mode INT0 to INT3 are not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 to INT3 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT x (x = 0, 1, 2, or 3) going from 0 to 1, INTx must then be held at 1 until the interrupt response sequence has been completed. If INTx is set to Level mode so as to release a Halt state, INTx must be held at 1 from the time INTx changes from 0 to 1 until the Halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INTx to revert to 0 before the Halt state has been INT0 to INT3 level mode released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H NOP NOP NOP EI INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. ; Changes from level to edge. ; Wait EI execution. LD (INTCLR), 0AH ; Clears interrupt request flag. Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. INT0 to INT 3: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input change from high to low after interrupt request has been generated in level mode. ("H" "L", "L" "H") INTRX: Instruction which read the receive buffer. 92CM22-48 2007-02-16 TMP92CM22 3.5 Port Function The TMP92CM22 features 50-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions of each port pin. Table 3.5.2 and Table 3.5.3 lists I/O registers and their specifications. Table 3.5.1 Port Function (R: U = with pull-up resistor) Port Names Port 1 Port 4 Port 5 Port 6 Port 7 Pin Names P10 to P17 P40 to P47 P50 to P57 P60 to P67 P70 P71 P72 P73 P74 P75 P76 P80 P81 P82 P83 P90 P91 P92 PA0 PA1 PA2 PA7 PC0 PC1 PC3 PC5 PC6 PD0 PD1 PD2 PD3 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 Number of Pins 8 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direction I/O I/O* I/O* I/O* Output Output Output Output Output Output I/O Output Output Output Output I/O I/O I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input Input Input Input Input Input Input R - - - - - - - - - - - - - - - - - - U U U U - - - - - - - - - - - - - - - - - - - - - - - - - Direction Setting Unit Bit Bit* Bit* Bit* (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Pin Names for Built-In Function D8 to D15 A0 to A7 A8 to A15 A16 to A23 RD WRLL WRLU CLKOUT R/ W WAIT Port 8 CS0 CS1 CS2 CS3 Port 9 SCK SO, SDA SI, SCL Port A Port C Port D Port F TA0IN INT1, TA1OUT INT0 INT2, TA3OUT INT3, TB0OUT0 INT4, TB1IN0 INT5, TB1IN1 TB1OUT0 TB1OUT1 TXD0 RXD0 SCLK0, CTS0 TXD1 RXD1 SCLK1, CTS1 Port G AN0 AN1 AN2 AN3, ADTRG AN4 AN5 AN6 AN7 *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. 92CM22-49 2007-02-16 TMP92CM22 Table 3.5.2 I/O Port Setting List (1/2) Ports Port 1 Input Pins P10 to P17 Input port Output port Specification I/O Register Setting Value Pn x x x x x x x x x x x x x PnCR PnFC PnODE 0 1 x 0* 1* x 0* 1* x 0* 1* x None 1 0 1 0 1 0 1 0 None None None 0 None D8 to D15 bus Port 4 P40 to P47 Input port* Output port* A0 to A7 output Port 5 P50 to P57 Input port* Output port* A8 to A15 output Port 6 P60 to P67 Input port* Output port* A16 to A23 output Port 7 P70 to P75 P70 P71 P72 P74 P75 P76 Output port RD output WRLL output WRLU output x None 1 None CLKOUT output R/ W output Input port Output port WAIT Input x x x x x x x x x x x x x x x x 0 1 0 0 0 1 0 1 Port 8 P80 to P83 P80 P81 P82 P83 Output port CS0 output CS1 output CS2 output CS3 output None 1 1 1 None Port 9 P90 to P92 P90 P91 P92 Input port Output port SCK input SCK output SO output SDA SI input SCL (Open drain) 0 1 0 x 1 x 0 x 0 0 0 1 1 1 0 1 0 0 0 0/1 0/1 1 0 1 X: Don't care *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. 92CM22-50 2007-02-16 TMP92CM22 Table 3.5.3 I/O Port Setting List (2/2) Ports Port A Port C Input Pins PA0, PA1, PA2, PA7 PC0, PC1, PC3, PC5, PC6 PC0 PC1 PC3 PC5 PC6 Input port Input port Output port TA0IN input Specification I/O Register Setting Value Pn x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x None None None PnCR None 0 1 x 1 0 x 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0/1 0 0 1 0 0/1 0 PnFC PnODE None 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 None 1 1 1 1 None 1 1 None None None None TA1OUT output INT1 input INT0 input INT2 input TA3OUT INT3 input TB0OUT0 Input port Output port TB1IN0, INT4 input TB1IN1, INT5 input TB0OUT0 output TB0OUT1 output Input port Output port TXD0 (Open drain) TXD0 RXD0 input SCLK0 input/output CTS0 input Port D PD0 to PD3 PD0 PD1 PD2 PD3 Port F PF0 to PF7 PF0 PF1 PF2 PF3 PF4 PF5 TXD1 (Open drain) TXD1 RXD1 input SCLK1 input/output CTS1 input Port G PG0 to PG7 PG3 Input port AN0 to AN7 input ADTRG input X: Don't care By resetting, these port pins become general-purpose input port. I/O pin is reset to input pin. When use built-in function, process all function by software. 92CM22-51 2007-02-16 TMP92CM22 3.5.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15). After released reset, device set port1 to pins of follow function by combination of AM1 and AM0 pins. AM1 AM0 0 0 1 1 0 1 0 1 Function Setting after Reset Don't use this setting Data bus (D8 to D15) Input port (P10 to P17) Don't use this setting Reset Direction control (on bit basis) P1CR write Function control (on byte batch) Internal data bus External access (Data write) P1FC write S Output latch A Selector P1 write D8 to D15 Output buffer B Port 1 P10 to P17 (D8 to D15) P1 Read External access (Data read) Figure 3.5.1 Port 1 92CM22-52 2007-02-16 TMP92CM22 Port 1 Register 7 P1 (0004H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is clear to "0".) Port 1 Control Register P1CR (0006H) 7 Bit symbol Read/Write After reset Function 0 P17C 6 P16C 0 5 P15C 0 4 P14C W 0 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 Refer to port 1 function setting Port 1 Function Register 7 Bit symbol P1FC (0007H) Read/Write After reset Function Refer to port 1 function setting 6 5 4 3 2 1 0 P1F W 0/1 Note3 Port 1 Function setting Note 1: Read-modify-write instruction is prohibited for registers P1FC and P1CR. Note 2: Figure 3.5.2 Register for Port 1 92CM22-53 2007-02-16 TMP92CM22 3.5.2 Port 4 (P40 to P47) Port 4 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC*. In addition to functioning as a general-purpose I/O port, port 4 can also function as a address bus (A0 to A7). After released reset, device set Port 4 to pins of follow function by combination of AM1 and AM0 pins. AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset Don't use this setting Address bus (A0 to A7) Address bus (A0 to A7) Don't use this setting Reset Internal address bus A0 to A7 Direction control (on bit basis)* P4CR write Function control Internal data bus (on bit basis) S B P4FC write Selector Output latch A Output buffer Port 4 P40 to P47 (A0 to A7) P4 write P4 read *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.3 Port 4 92CM22-54 2007-02-16 TMP92CM22 7 P4 (0010H) Bit symbol Read/Write After reset P47 6 P46 5 Port 4 Register 4 P44 R/W 3 P43 2 P42 1 P41 0 P40 P45 Data from external port (Output latch register is cleared to "0".) 7 P4CR (0012H) Bit symbol Read/Write After reset Function 0 P47C 6 P46C 0 Port 4 Control Register 5 4 3 P45C 0 P44C W 0 0 P43C 2 P42C 0 1 P41C 0 0 P40C 0 0: Input 1: Output (Note2) 7 P4FC (0013H) Bit symbol Read/Write After reset Function 1 P47F 6 P46F 1 Port 4 Function Register 5 4 3 P45F 1 P44F W 1 1 P43F 2 P42F 1 1 P41F 1 0 P40F 1 0: Port 1: Address bus (A0 to A7) Note1: Read-modify-write instruction is prohibited for registers P4CR and P4FC. Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.4 Register for Port 4 92CM22-55 2007-02-16 TMP92CM22 3.5.3 Port 5 (P50 to P57) Port 5 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P5CR and function register P5FC*. In addition to functioning as a general-purpose I/O port, port 5 can also function as an address bus (A8 to A15). After released reset, device set port 5 to pins of follow function by combination of AM1 and AM0 pins. AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset Don't use this setting Address bus (A8 to A15) Address bus (A8 to A15) Don't use this setting Reset Internal address bus A8 to A15 Direction control (on bit basis)* P5CR write Internal data bus Function control (on bit basis) S B P5FC write Selector Output latch A Output buffer Port 5 P50 to P57 (A8 to A15) P5 write P5 read *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.5 Port 5 92CM22-56 2007-02-16 TMP92CM22 7 P5 (0014H) Bit symbol Read/Write After reset P57 6 P56 5 Port 5 Register 4 P54 R/W 3 P53 2 P52 1 P51 0 P50 P55 Data from external port (Output latch register is cleared to "0".) 7 P5CR (0016H) Bit symbol Read/Write After reset Function 0 P57C 6 P56C 0 Port 5 Control Register 5 4 3 P55C 0 P54C W 0 0 P53C 2 P52C 0 1 P51C 0 0 P50C 0 0: Input 1: Output (Note2) 7 P5FC (0017H) Bit symbol Read/Write After reset Function 1 P57F 6 P56F 1 Port 5 Function Register 5 4 3 P55F 1 P54F W 1 1 P53F 2 P52F 1 1 P51F 1 0 P50F 1 0: Port 1: Address bus (A8 to A15) Note1: Read-modify-write instruction is prohibited for registers P5CR and P5FC. Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.6 Register for Port 5 92CM22-57 2007-02-16 TMP92CM22 3.5.4 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC*. In addition to functioning as a general-purpose I/O port, port 6 can also function as an address bus (A16 to A23). After released reset, device set port 6 to pins of follow function by combination of AM1 and AM0 pins. AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset Don't use this setting Address bus (A16 to A23) Address bus (A16 to A23) Don't use this setting Reset Internal address bus A16 to A23 Direction control (on bit basis)* P6CR write Internal data bus Function control (on bit basis) S B P6FC write Selector Output latch A Output buffer Port 6 P60 to P67 (A16 to A23) P6 write P6 read *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.7 Port 6 92CM22-58 2007-02-16 TMP92CM22 Port 6 Register 7 P6 (0018H) Bit symbol Read/Write After reset P67 6 P66 5 P65 4 P64 R/W 3 P63 2 P62 1 P61 0 P60 Data from external port (Output latch register is cleared to "0".) Port 6 Control Register 7 P6CR (001AH) Bit symbol Read/Write After reset Function 0 0 0 0 P67C 6 P66C 5 P65C 4 P64C W 3 P63C 0 2 P62C 0 1 P61C 0 0 P60C 0 0: Input 1: Output (Note2) Port 6 Function Register 7 P6FC (001BH) Bit symbol Read/Write After reset Function 1 1 1 1 P67F 6 P66F 5 P65F 4 P64F W 3 P63F 1 2 P62F 1 1 P61F 1 0 P60F 1 0: Port 1: Address bus (A16 to A23) Note1: Read-modify-write instruction is prohibited for registers P6CR and P6FC. Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.8 Register for Port 6 92CM22-59 2007-02-16 TMP92CM22 3.5.5 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port (P70 to P75 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P73 pins can also function as output pin of read/write strobe signals to connect with an external memory. P74 pin can also function as CLKOUT output pin when outputted internal clock. P76 pin can also function as wait input. After reset, P71 to P75 pins are set to output port mode, and P76 pin is set to input port mode. P70 pin set port 1 to pins of follow function by combination of AM1 and AM0 pins. AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset Don't use this setting CPU control pin ( RD ) CPU control pin ( RD ) Don't use this setting Reset Function control (on bit basis) Internal data bus P7FC write S Output latch A Selector P7 write B Output buffer Port 7 P70 ( RD ) P71 ( WRLL ) P72 ( WRLU ) P73 P74 (CLKOUT) P75 (R/ W ) P7 read RD , WRLL , WRLU , CLKOUT, R/ W Note: P73 is fixed to VCC. Figure 3.5.9 Port 7 (P70 to P75) 92CM22-60 2007-02-16 TMP92CM22 Reset Direction control (on bit basis) P7CR write Internal data bus Function control (on bit basis) P7FC write S Output latch Output buffer P7 write Port P7 P76 ( WAIT ) P7 read Internal WAIT signal Figure 3.5.10 Port 7 (P76) Port 7 Register 7 P7 (001CH) Bit symbol Read/Write After reset Data from external port (Note) 6 P76 5 P75 1 4 P74 1 3 P73 R/W 1 2 P72 1 1 P71 1 0 P70 1 Note: Output latch register is cleared to 0. Port 7 Control Register 7 P7CR (001EH) Bit symbol Read/Write After reset Function 6 P76C W 0 0: Input 1: Output 5 4 3 2 1 0 Port 7 Function Register 7 P7FC (001FH) Bit symbol Read/Write After reset Function 0 0: Port 1: WAIT 0 0: Port 1: R/ W 0 0: Port 6 P76F 5 P75F 4 P74F 3 P73F W 0 0: Port 2 P72F 0 0: Port 1 P71F 0 0: Port 1: WRLL 0 P70F 1 0: Port 1: RD 1: CLKOUT 1: Don't set 1: WRLU Note: Read-modify-write instruction is prohibited for registers P7CR and P7FC. Figure 3.5.11 Register for Port 7 92CM22-61 2007-02-16 TMP92CM22 3.5.6 Port 8 (P80 to P83) Port 8 is 4-bit output port. Resetting sets output latch of P82 to "0" and set output latches of P80, P81, and P83 to "1". In addition to functioning as a output port, port 8 can also function as a output chip select signal ( CS0 to CS3 ). These settings operate by programming "1" to the corresponding bit of P8FC. Resetting set all bits of P8FC to "0", these pits set output mode. Reset Function control (on bit basis) Internal data bus P8FC write S Output latch A Selector P8 write B P80 ( CS0 ) P81 ( CS1 ) P82 ( CS2 ) P83 ( CS3 ) P8 read CS0 , CS1 , CS2 , CS3 Figure 3.5.12 Port 8 Port 8 Register 7 P8 (0020H) Bit symbol Read/Write After reset 1 0 6 5 4 3 P83 2 P82 R/W 1 P81 1 0 P80 1 Port 8 Function Register 7 Bit symbol P8FC (0023H) Read/Write After reset Function 0 0: Port 1: CS3 0 0: Port 1: CS2 6 5 4 3 P83F 2 P82F W 1 P81F 0 0: Port 1: CS1 0 P80F 0 0: Port 1: CS0 Note 1: Read-modify-write instruction is prohibited for the registers P8FC. Note 2: When set P82 pin as CS2 after release reset, set function register (P8FC Figure 3.5.13 Register for Port 8 92CM22-62 2007-02-16 TMP92CM22 3.5.7 Port 9 (P90 to P92) Port 9 is 3-bit general-purpose I/O port. Each bit can be set individually for input or output. In addition to functioning as a general-purpose I/O port, port 9 can also function as a serial bus interface input (SCK (Clock signal in SIO mode), SO (Data output signal in SIO mode), SDA (Data signal in I2C bus mode), SI (Data input signal in SIO mode) and SCL (Clock signal in I2C bus mode)). These settings operate by programming to the corresponding bit of P9FC. Resetting set value of P9CR and P9FC to "0", all bits are set to input port. And all bits of output latch are set to "1". Reset Direction control (on bit basis) P9CR write Internal data bus Function control (on bit basis) P9FC write S Output latch S A Selector B P90 (SCK), Open-drain enable P9ODE P91 (SO/SDA) P92 (SI/SCL) P9 write SCK output SO output SDA output SCL output S B Selector A P9 read SCK input SDA input SI/SCL input Figure 3.5.14 Port 9 (P90 to P92) 92CM22-63 2007-02-16 TMP92CM22 Port 9 Register 7 P9 (0024H) Bit symbol Read/Write After reset 6 5 4 3 2 P92 1 P91 R/W 0 P90 Data from external port (Output latch register is set to 1) Port 9 Control Register 7 P9CR (0026H) Bit symbol Read/Write After reset Function 0 0: Input 6 5 4 3 2 P92C 1 P91C W 0 1: Output 0 P90C 0 Port 9 Function Register 7 P9FC (0027H) Bit symbol Read/Write After reset Function 0 0: Port, SI 1: SCL Note 6 5 4 3 2 P92F 1 P91F W 0 0: Port 1: SO, SDA 0 P90F 0 0: Port, SCK input 1:SCK output Note Port 9 ODE Register 7 P9ODE (0025H) Bit symbol Read/Write After reset Function 0 1:Open drain 6 5 4 3 2 P92ODE W 1 P91ODE 0 1:Open drain 0 Note1: Read-modify-write instruction is prohibited for the registers P9CR, P9FC, and P9ODE. Note2: When using SI and SCK input function, set P9FC Figure 3.5.15 Register for Port 9 92CM22-64 2007-02-16 TMP92CM22 3.5.8 Port A (PA0 to PA2, PA7) Port A is 4-bit general-purpose input port with pull-up resistor. Pull-up resistor Internal data bus PA0, PA1, PA2, PA7 PA read Figure 3.5.16 Port A Port A Register 7 PA (0028H) Bit symbol Read/Write After reset PA7 R Data from external port 6 5 4 3 2 PA2 1 PA1 R Data from external port 0 PA0 Figure 3.5.17 Register for Port A 92CM22-65 2007-02-16 TMP92CM22 3.5.9 Port C (PC0, PC1, PC3, PC5, and PC6) Port C is 5-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port C to input port. In addition to functioning as a general-purpose I/O port, port C can also function as a input/output pin (TA0IN, TA1OUT, TA3OUT, and TB0OUT0) and external interrupt pin (INT0 to INT3). These settings operate by programming "1" to the corresponding bit of PCCR and PCFC. Resetting resets the PCCR and PCFC to "0", and sets all bits to input port. (1) PC0 (TA0IN) In addition to function as I/O port, port PC0 can also function as input pin TA0IN of timer channel 0. Reset Direction control (on bit basis) PCCR write Internal data bus Function control (on bit basis) PCFC write S Output latch PC0 (TA0IN) PC write S B Selector A PC read TA0IN Note: Can not read the output latch data when output mode. Figure 3.5.18 Port C (PC0) 92CM22-66 2007-02-16 TMP92CM22 (2) PC1 (INT1, TA1OUT), PC5 (INT2, TA3OUT), PC6 (INT3, TB0OUT0) In addition to function as I/O port, port PC1, PC5, and PC6 can also function as external interrupt input pin INT1 to INT3 and output pin of timer channel TA1OUT, TA3OUT, and TB0OUT0. Reset Direction control (on bit basis) PCCR write Function control (on bit basis) Internal data bus PCFC write S Output latch PC write TA1OUT TA3OUT TB0OUT0 S B Selector A S A Selector B PC1 (INT1, TA1OUT) PC5 (INT2, TA3OUT) PC6 (INT3, TB0OUT0) PC read INT1 INT2 INT3 A Selector S B Select rising/falling IIMC High level/low level selection IIMC2 Note: Can not read the output latch data when output mode. Figure 3.5.19 Port C (PC1, PC5, and PC6) 92CM22-67 2007-02-16 TMP92CM22 (3) PC3 (INT0) In addition to function as I/O port, port PC3 can also function as external interrupt pin INT0. Reset Direction control (on bit basis) PCCR write Internal data bus Function control (on bit basis) PCFC write S Output latch PC3 (INT0) PC read S B Selector PC read INT0 A Select level/edge and Select rising/falling IIMC Figure 3.5.20 Port C (PC3) 92CM22-68 2007-02-16 TMP92CM22 Port C Register 7 PC (0030H) Bit symbol Read/Write After reset 6 PC6 R/W 5 PC5 4 3 PC3 R/W Data from external port (Note) 2 1 PC1 R/W 0 PC0 Data from external port (Note) Data from external port (Note) Note: Output latch register is set to 1. Port C Control Register 7 PCCR (0032H) Bit symbol Read/Write After reset Function 0 6 PC6C W 5 PC5C 0 4 3 PC3C W 0 0: Input 1: Output 2 1 PC1C W 0 0 PC0C 0 0: Input 1: Output 0: Input 1: Output Port C Function Register 7 PCFC (0033H) Bit symbol Read/Write After reset Function 0 0: Port 1: INT3 TB0OUT0 6 PC6F W 5 PC5F 0 0: Port 1: INT2 TA3OUT 4 3 PC3F W 1 0: Port 1: INT0 2 1 PC1F W 0 0: Port 1: INT1 TA1OUT 0 PC0F 0 0: Port 1: TA0IN INT1, TA1OUT setting 0 Input port INT1 1 Output port TA1OUT 0 1 INT2, TA3OUT Setting 0 Input port INT2 1 Output port TA3OUT 0 1 INT3, TB0OUT0 setting 0 Input port INT3 1 Output port TB0OUT0 0 1 Note 1: Read-modify-write instruction is prohibited for the registers PCCR and PCFC. Note 2: PC0/TA0IN pins do not have a register changing PORT/FUNCTION. For example, when it is used as an input port, the input signal is inputted to 8-bit timer as the input 0. Note 3: Can not read the output latch data when PC0, PC1, PC5, and PC6 are output mode. Figure 3.5.21 Register for Port C 92CM22-69 2007-02-16 TMP92CM22 3.5.10 Port D (PD0 to PD3) Port D is 4-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port D to input port. In addition to functioning as a general-purpose I/O port, port D can also function as an input pin (INT4 and INT5)/output pin (TB0IN, TB1OUT, TB3OUT, and TB1OUT1). These settings operate by programming "1" to the corresponding bit of PDCR and PDFC. Resetting resets the PDCR and PDFC to "0", and sets all bits to input port. (1) PD0 (INT4, TB1IN0), PD1 (INT5, TB1IN1) In addition to function as I/O port, port PD0 and PD1 can also function as external interrupt input pins INT4, INT5, timer channel input pins TB1IN0 and TB1IN1. Reset Direction control (on bit basis) PDCR write Internal address bus Function control (on bit basis) PDFC write S Output latch PD0 (INT4, TB1IN0) PD1 (INT5, TB1IN1) PD write S B Selector PD read INT4, TB1IN0 INT5, TB1IN1 A Note: Can not read the output latch data when output mode. Figure 3.5.22 Port D (PD0 and PD1) 92CM22-70 2007-02-16 TMP92CM22 (2) PD2 (TB1OUT0) and PD3 (TB1OUT1) In addition to function as I/O port, port PD0 and PD1 can also function as timer channel output pins TB1OUT0 and TB1OUT1. Reset Direction control (on bit basis) PDCR write Internal data bus Function control (on bit basis) PDFC write S Output latch S A Selector B S B Selector A PD2 (TB1OUT0) PD3 (TB1OUT1) PD write TB1OUT0 TB1OUT1 PF read Figure 3.5.23 Port D (PD2 and PD3) 92CM22-71 2007-02-16 TMP92CM22 Port D Register 7 PD (0034H) Bit symbol Read/Write After reset 6 5 4 3 PD3 2 PD2 R/W 1 PD1 0 PD0 Data from external port (Output latch register is set to 1) Port D Control Register 7 PDCR (0036H) Bit symbol Read/Write After reset Function 0 0: Input 1: Output 0 0: Input 1: Output 6 5 4 3 PD3C 2 PD2C W 1 PD1C 0 0: Input 1: Output 0 PD0C 0 0: Input 1: Output Port D I/O setting 0 1 Input Output 7 PDFC (0037H) Bit symbol Read/Write After reset Function 6 Port D Function Register 5 4 3 PD3F 0 2 PD2F W 0 1 PD1F 0 0 PD0F 0 0: Port 1: TB0IN0 INT4 Input 0: Port 0: Port 0: Port 1: TB1OUT1 1: TB1OUT0 1: TB0IN1 INT5 Input PD2 output setting asTB1OUT0 PDFC PDCR PDFC 1 1 Note 1: Read-modify-write instruction is prohibited for the registers PDFC and PDCR. Note 2: Can not read the output latch data when PD0 and PD1 are output mode. Figure 3.5.24 Register for Port D 92CM22-72 2007-02-16 TMP92CM22 3.5.11 Port F (PF0 to PF7) Port F is 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting resets the PFCR and PFFC to "0", and sets all bits to input port. And all bits of output latch register to "1". In addition to functioning as a general-purpose I/O port, port F can also function as I/O function of serial channel 0 and 1. These settings operate by writing "1" to the corresponding bit of PFFC. Resetting resets the PDCR and PDFC to "0", and sets all bits to input port. (1) Port PF0 and PF3 (TXD0/TXD1) In addition to function as I/O port, port PF0 and PF3 can also function as TXD output pin of serial channel. Thus, output buffer feature a programmable open-drain function, and setting enable by PFFC Reset Direction control (on bit basis) PFCR write Internal data bus Function control (on bit basis) PFFC write S Output latch TXD0, TXD1 PF write S B Selector A S A Selector B PF0 (TXD0) PF3 (TXD1) Open-drain enable PF read Figure 3.5.25 Port F (PF0 and PF3) 92CM22-73 2007-02-16 TMP92CM22 (2) Ports PF1 and PF4 (RXD0 and XD1) In addition to function as I/O port, port PF1 and PF4 can also function as RXD input pin of serial channel. Reset Direction control (on bit basis) PFCR write Internal data bus S Output latch PF1 (RXD0) PF4 (RXD1) S B Selector A PF write PF read RXD0, RXD1 Figure 3.5.26 Port F (PF and PF4) 92CM22-74 2007-02-16 TMP92CM22 (3) Port PF2 ( CTS0 , SCLK0) and port PF5 ( CTS1 , SCLK1) In addition to function as I/O port, port PF2 and PF5 can also function as CTS input pin of serial channel or SCLK I/O pin. Reset Direction control (on bit basis) PFCR write Internal data bus Function control (on bit basis) PFFC write S Output latch SCLK0, SCLK1 output PF write S A Selector B S B Selector A PF2 (SCLK0, CTS0 ) PF5 (SCLK1, CTS1 ) PF read CTS0 , CTS1 SCLK0, SCLK1 input Figure 3.5.27 Port F (PF2 and PF5) (4) Port PF6 and port PF7 These ports are general-purpose I/O port. Reset R Direction control (on bit basis) Internal data bus PFCR write S Output latch PF6 to PF7 PF write S B Selector A PF read Figure 3.5.28 Port F (PF6 and PF7) 92CM22-75 2007-02-16 TMP92CM22 Port F Register 7 PF (003CH) Bit symbol Read/Write After reset PF7 6 PF6 5 PF5 4 PF4 R/W 3 PF 2 PF2 1 PF1 0 PF0 Data from external port (Output latch register is set to 1) Port F Control Register 7 PFCR (003EH) Bit symbol Read/Write After reset Function 0 0 0 0 0: Input PF7C 6 PF6C 5 PF5C 4 PF4C W 3 PF3C 0 1: Output 2 PF2C 0 1 PF1C 0 0 PF0C 0 Port F Function Register 7 PFFC (003FH) Bit symbol Read/Write After reset Function 0 Always write "0". - 6 - W 0 Always write "0". 5 PF5F 0 0: Port 1: SCLK1 output 4 3 PF3F W 0 0: Port 1: TXD1 2 PF2F 0 0: Port 1: SCLK0 output 1 0 PF0F W 0 0: Port 1: TXD0 Port function setting 0 Input port TXD1 (Open drain) 1 Output port TXD1 0 1 0 Input port TXD0 (Open drain) 1 Output port TXD0 0 1 Note 1: Read-modify-write instruction is prohibited for the registers PFCR and PFFC. Note 2: PF1/RXD0 and PF4/RXD1 pins do not have a register changing PORT/FUNCTION. For example, when it is used as an input port, the input signal is inputted to SIO as the serial receive data. Note 3: PF0 and PF3 pins do not have a register (PFODE) for open-drain setting. Please conduct the open-drain setting according to above setting. Figure 3.5.29 Register for Port F 92CM22-76 2007-02-16 TMP92CM22 3.5.12 Port G (PG0 to PG7) Port G is 8-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the AD converter. Internal data bus PG read Convertion result register AD converter Channel selector Port G PG0 to PG7 (AN0 to AN7) AD read ADTRG (only PG3) Figure 3.5.30 Port G Port G Register 7 PG (0040H) Bit symbol Read/Write After reset PG7 6 PG6 5 PG5 4 PG4 R 3 PG3 2 PG2 1 PG1 0 PG0 Data from external port Note: The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode register ADMOD1. Figure 3.5.31 Register for Port G 92CM22-77 2007-02-16 TMP92CM22 3.6 Memory Controller Function TMP92CM22 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for 4-block address area. (2) Connecting memory specifications Specifies SRAM and ROM as memories to connect with the selected address areas. (3) Data bus size selection Whether 8-bit or 16-bit is selected as the data bus size of the respective block address areas. (4) Wait control Wait specification bit in the control register and WAIT input pin control the number of waits in the external bus cycle. Read cycle and write cycle can specify the number of waits individually. The number of waits is controlled in 6 mode mentioned below. 0 waits, 1 wait, 2 waits, 3 waits, 4 waits N waits (Control with WAIT pin) 3.6.1 92CM22-78 2007-02-16 TMP92CM22 3.6.2 Control Register and Operation after Reset Release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control register The control registers of the memory controller are as follows. * Control register: BnCSH/BnCSL (n = 0 to 3, EX) Sets the basic functions of the memory controller, that is the connecting memory type, the number of waits to be read and written. Memory start address register: MSARn (n = 0 to 3) Sets a start address in the selected block address areas. Memory address mask register: MAMRn (n = 0 to 3) Sets a block size in the selected address areas. * * In addition to setting of the above-mentioned registers, it is necessary to set the following registers to control ROM page mode access. * Page ROM control register: PMEMCR Sets to executed ROM page mode accessing. (2) Operation after reset release The start data bus width is determined depending on state of AM1 and AM0 pins just after reset release. Then, the external memory is accessed as follows. AM1 0 0 1 1 AM0 0 1 0 1 Start Mode Don't use this setting Start with 16-bit data bus Start with 8-bit data bus Don't use this setting AM1/AM0 pins are valid only just after reset release. In the other cases, the data bus width is set to the value set to BnBUS bit of the control register. By reset, only control register (B2CSH/B2CSL) of the block address area 2 is automatically effective (B2CSH 92CM22-79 2007-02-16 TMP92CM22 3.6.3 Basic Functions and Register Setting In this section, setting of the block address area, the connecting memory and the number of waits out of the memory controller's functions are described. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSAR) sets the start address of the block address areas. The memory controller compares between the register value and the address every bus cycles. The address bit which is masked by the memory address mask register (MAMR) is not compared by the memory controller. The block address area size is determined by setting the memory address mask register. The set value in the register is compared with the block address area on the bus. If the compared result is a match, the memory controller sets the chip select signal ( CS ) to "low". (i) Setting memory start address register The MS23 to MS16 bits of the memory start address register respectively correspond with addresses A23 to A16. The lower start address A15 to A0 are always set to address 0000H. Therefore the start address of the block address area are set to addresses 000000H to FF0000H every 64 Kbytes. (ii) Setting memory address mask registers The memory address mask register sets whether an address bit is compared or not. Set the register to "0" to compare, or to "1" not to compare. The address bit to be set is depended on the block address area. Block address area 0: A20 to A8 Block address area 1: A21 to A8 Block address area 2 to 3: A22 to A15 The above-mentioned bits are always compared. The block address area size is determined by the compared result. The size to be set depending on the block address area is as follows. Size (bytes) CS area 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M CS0 CS1 CS2 to CS3 Note: After reset release, only the control register of the block address area 2 is valid. The control register of the block address area 2 has 92CM22-80 2007-02-16 TMP92CM22 (iii) Example of register setting To set the block address area 1 to 512 bytes from address 110000H, set the register as follows. MSAR1 Register 7 Bit symbol Setting value M1S23 0 6 M1S22 0 5 M1S21 0 4 M1S20 1 3 M1S19 0 2 M1S18 0 1 M1S17 0 0 M1S16 1 M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with address A23 to A16. A15 to A0 are cleared to "0". Therefore setting MSAR1 to the above-mentioned value specifies the start address of the block address area to address 110000H. The start address is set as it is in the other block address areas. MAMR1 Register 7 Bit symbol Setting value M1V21 0 6 M1V20 0 5 M1V19 0 4 M1V18 0 3 M1V17 0 2 M1V16 0 1 M1V15-9 0 0 M1V8 1 M1V21 to M1V16 and M1V8 bits of the memory address mask register MAMR1 set whether address A21 to A16 and A8 are compared or not. Set the register to "0" to compare, or to "1" not to compare. A23 and A22 are always compared. Setting the above-mentioned compares A23 to A9 with the values set as the start addresses. Therefore 512 bytes of addresses 110000H to 1101FFH are set as the block address area 1, and compared with the addresses on the bus. If the compared result is a match, the chip select signal CS1 is set to "low". The other block address area sizes are specified like this. Similarly, A23 is always compared in block address areas 2 to 3. Whether A22 to A15 are compared or not is set to register. Note: When the set block address area overlaps with the built-in memory area, or both two address areas overlap, the block address area is processed according to priority as follows. Built-in I/O > Built-in memory > Block address area 0 >1 > 2 > 3 > CSEX Also that any accessed areas outside the address spaces set by CS0 to CS3 are processed as the CSEX space. Therefore, settings of CSEX apply for the control of wait cycles, data bus width, etc. 92CM22-81 2007-02-16 TMP92CM22 (2) Connection memory specification Setting the BnOM1 to BnOM0 bit of the control register (BnCSH) specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows. TMP92CM22 prohibit changing default (SRAM/ROM). BnOM1, BnOM0 Bit (BnCSH register) BnOM1 0 0 1 1 BnOM0 0 1 0 1 Function SRAM/ROM (Default) (Reserved) (Reserved) (Reserved) (3) Data bus width specification The data bus width is set for every block address area. The bus size is set by the BnBUS1 and BnBUS0 bits of the control register (BnCSH) as follows. BnBUS Bit (BnCSH register) BnBUS1 0 0 1 1 BnBUS0 0 1 0 1 Function 8-bit bus mode (Default) 16-bit bus mode (Reserved) (Reserved) This way of changing the data bus size depending on the address being accessed is called "dynamic bus sizing". The part where the data is output to is depended on the data size, the bus width and the start address. Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus width are put in consecutive addresses, do not execute an access to placed on both memories with one command. 92CM22-82 2007-02-16 TMP92CM22 Data Size (Bit) 8 Start Address 4n + 0 4n + 1 4n + 2 4n + 3 Data Width in Memory Side (Bit) 8/16 8 16 8/16 8 16 8 16 CPU Address 4n + 0 4n + 1 4n + 1 4n + 2 4n + 3 4n +3 (1) 4n + 0 (2) 4n + 1 4n + 0 (1) 4n + 1 (2) 4n + 2 (1) 4n + 1 (2) 4n + 2 (1) 4n + 2 (2) 4n + 1 4n + 2 (1) 4n + 3 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (1) 4n + 0 (2) 4n + 1 (3) 4n + 2 (4) 4n + 3 CPU Data D15 to D8 xxxxx xxxxx b7 to b0 xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 xxxxx b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 b7 to b0 B15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 16 4n + 0 4n + 1 8 16 4n + 2 8 16 4n + 3 8 16 32 4n + 0 8 16 4n + 1 8 (1) 4n + 0 (2) 4n + 2 (1) 4n + 0 (2) 4n + 1 (3) 4n + 2 (4) 4n + 3 16 (1) 4n + 1 (2) 4n + 2 (3) 4n + 4 4n + 2 8 (1) 4n + 2 (2) 4n + 3 (3) 4n + 4 (4) 4n + 5 16 4n + 3 8 (1) 4n + 2 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (3) 4n + 5 (4) 4n + 6 16 (1) 4n + 3 (2) 4n + 4 (3) 4n + 6 xxxxx: During a read, data input to the bus ignored. At write, the bus is at high impedance and the write strobe signal remains inactive. 92CM22-83 2007-02-16 TMP92CM22 (4) Wait control The external bus cycle completes a wait of two states at least (100 ns at fSYS = 20 MHz). Setting the 0 0 1 1 1 0 BnWR1 BnWW1 0 1 0 1 1 1 Others BnWW0 BnWR0 1 0 1 0 1 1 2 states (0 waits) 3 states (1 wait) 4 states (2 waits) 5 states (3 waits) 6 states (4 waits) (Reserved) Function access fixed mode access fixed mode (Default) access fixed mode access fixed mode access fixed mode WAIT pin input mode (i) Waits number fixed mode The bus cycle is completed with the set states. The number of states is selected from 2 states (0 waits) to 6 states (4 waits). (ii) WAIT pin input mode This mode samples the WAIT input pins. It continuously samples the WAIT pin state and inserts a wait if the pin is active. The bus cycle is minimum 2 states. The bus cycle is completed when the wait signal is non-active ("High" level) at 2 states. The bus cycle extends if the wait signal is active at 2 states and more. If a lot of connected pertain ROM and etc. (Much data-output-floating-time (tDF)), each other's data-bus-output-recovery-time is trouble. However, by setting BnREC of control register (BnCSH), can to insert dummy cycle of 1-state just before first bus cycle of starting access another block address. BnREC Bit (BnCSH register) 0 1 No dummy cycle is inserted (Default). Dummy cycle is inserted. 92CM22-84 2007-02-16 TMP92CM22 * CLKOUT Address CSm When not inserting a dummy (0 waits) CSn RD * When inserting a dummy cycle (0 waits) Dummy CLKOUT Address CSm CSn RD 92CM22-85 2007-02-16 TMP92CM22 (5) Bus access timing * External read/write bus cycle (0 waits) T1 T2 CLKOUT (20 MHz) CS Address RD Read D7 to D0 WR input Write output D7 to D0 * External read/write bus cycle (1 wait) T1 TW T2 CLKOUT (20 MHz) CS Address RD Read D7 to D0 WR Input Write Output D7 to D0 92CM22-86 2007-02-16 TMP92CM22 * External read/write bus cycle (0 waits at WAIT pin input mode) T1 T2 CLKOUT (20 MHz) CS Address RD Read D7 to D0 WR Input Write Output D7 to D0 WAIT Sampling * External read/write bus cycle (n waits at WAIT pin input mode) CLKOUT (20 MHz) CS T1 TW T2 Address RD Read D7 to D0 WR Input Write Output D7 to D0 WAIT Sampling Sampling 92CM22-87 2007-02-16 TMP92CM22 Example of WAIT input cycle (5 waits) FF0 D CK RES Q FF1 D CK RES Q FF2 D CK RES Q FF3 D CK RES Q FF4 D CK RES Q WAIT CLKOUT CSn RD WRLL WRLU CLKOUT (20 MHz) CSn 1 2 3 4 5 6 7 RD FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q WAIT 92CM22-88 2007-02-16 TMP92CM22 (6) Connecting external memory Figure 3.6.1 shows an example of how to connect external memory to the TMP92CM22. This example connects ROM and SRAM in 16-bit width. TMP92CM22 RD 16-bit SRAM OE LB WRLL WRLU UB R/ W CS0 R/W CE D [15:0] A0 A1 A2 A3 I/O [16:1] Not connetion A0 A1 A2 16-bit ROM OE CS2 CE DQ [15:0] A0 A1 A2 Figure 3.6.1 Example of External Memory By resetting, TMP92CM22 function as output port. Output latch of P82 ( CS2 ) is cleared to "0", and output "L". Output latch of P80 ( CS0 ), P81 ( CS1 ) and P83 ( CS3 ) are set to "1", and output "H". When set port 8 from port function to CS function, set need bit of P8FC register to "1". Note: When set P82 as CS2 after release reset, set function register remain output latch of P82 is "0" (P8 92CM22-89 2007-02-16 TMP92CM22 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers The TMP92CM22 supports ROM access of the page mode. ROM access of the page mode is specified only in block address area 2. ROM page mode is set by the page ROM control register (PMEMCR). Setting OPWR1/OPWR0 Bit (PMEMCR register) OPWR1 0 0 1 1 OPWR0 0 1 0 1 Number of Cycle in A Page 1 state (n-1-1-1 mode) (n 2) 2 states (n-2-2-2 mode) (n 3) 3states (n-3-3-3 mode) (n 4) (Reserved) Note: Set the number of waits ("n") using the control register (BnCSL) in each block address area. The page size (The number of bytes) of ROM in the CPU side is set by the PR1 0 0 1 1 PR0 0 1 0 1 ROM Page Size 64 bytes 32 bytes 16 bytes 8 bytes (2) Signal pulse CLKOUT tCYC A0 to A23 CS2 +0 +1 +2 +3 tAD3 RD tAD2 tAD2 tAD2 tHA tAD3 D0 to D31 Data input tHA Data input tHA Data input tHA Data input tHR Figure 3.6.2 Page mode access Timing (8-byte example) 92CM22-90 2007-02-16 TMP92CM22 3.6.5 List of Registers The memory control registers and the settings are described as follows. For the addresses of the registers, see list of special function registers in section 5. (1) Control registers The control register is a pair of BnCSL and BnCSH. ("n" is a number of the block address area.) BnCSL has the same configuration regardless of the block address areas. In BnCSH, only B2CSH which is corresponded to the block address area 2 has a different configuration from the others. BnCSL 7 Bit symbol Read/Write After reset BnWW[2:0] 0 6 BnWW2 5 BnWW1 W 1 4 BnWW0 0 3 2 BnWR2 0 1 BnWR1 W 1 0 BnWR0 0 Specifies the number of write waits. 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 111 = 6 states (4 waits) access Others = (Reserved) BnWR[2:0] Specifies the number of read waits. 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 111 = 6 states (4 waits) access Others = (Reserved) 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode B2CSH 7 Bit symbol Read/Write After reset B2E 1 B2E W 0 0 0 6 B2M 5 4 B2REC 3 B2OM1 2 B2OM0 W 0 1 B2BUS1 0 0 B2BUS0 0 Enable bit. 0 = No chip select signal output 1 = Chip select signal output (Default) Note: B2M After reset release, only the enable bit B2E of B2CSH register is valid ("1"). Specifies the block address area. 0 = Sets the block address area of CS2 to addresses 000000H to FFFFFFH (Default) 1 = Sets the block address area of CS2 to programmable Note: After reset release, the block address area 2 is set to addresses 000000H to FFFFFFH. 92CM22-91 2007-02-16 TMP92CM22 B2REC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cycle B2OM[1:0] 00 = SRAM or ROM (Default) Others = (Reserved) B2BUS[1:0] Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = (Reserved) 11 = (Reserved) Note: The value of B2BUS bit is set according to the state of AM[1:0] pin after reset release. BnCSH (n = 0, 1, 3) 7 Bit symbol Read/Write After reset BnE Enable bit. 0 = No chip select signal output (Default) 1 = Chip select signal output Note: After reset release, only the enable bit B2E of B2CSH register is valid ("1"). BnREC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cycle BnOM[1:0] 00 = SRAM or ROM (Default) 01 = (Reserved) 10 = (Reserved) 11 = (Reserved) BnBUS[1:0] Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = (Reserved) 11 = (Reserved) BnE W 0 0 0 6 5 4 BnREC 3 BnOM1 2 BnOM0 W 0 1 BnBUS1 0 0 BnBUS0 0 92CM22-92 2007-02-16 TMP92CM22 BEXCSL 7 Bit symbol Read/Write After reset 0 6 BEXWW2 5 BEXWW1 W 1 4 BEXWW0 0 3 2 BEXWR2 0 1 BEXWR1 W 1 0 BEXWR0 0 BEXWW[2:0] Specifies the number of write waits. 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 111 = 6 states (4 waits) access Others = (Reserved) BEXWR[2:0] Specifies the number of read waits. 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 111 = 6 states (4 waits) access Others = (Reserved) 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode BEXCSH 7 Bit Symbol Read/Write After reset BEXOM[1:0] 00 = SRAM or ROM (Default) 01 = (Reserved) 10 = (Reserved) 11 = (Reserved) BEXBUS[1:0] 00 = 8 bits (Default) 01 = 16 bits 10 = (Reserved) 11 = (Reserved) 6 - 5 - W Always write 0. 4 - 3 BEXOM1 0 2 BEXOM0 W 0 1 BEXBUS1 0 0 BEXBUS0 0 92CM22-93 2007-02-16 TMP92CM22 (1) Block address area specification register A start address and range in the block address are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The memory start address register sets all start address similarly regardless of the block address areas. The bit to be set by the memory address mask register is depended on the block address area. MSARn (n = 0 to 3) 7 Bit symbol Read/Write After reset MnS<23:16> Sets a start address. Sets the start address of the block address areas. The bit is corresponding to the address A23 to A16. 1 1 1 1 MnS23 6 MnS22 5 MnS21 4 MnS20 R/W 3 MnS19 1 2 MnS18 1 1 MnS17 1 0 MnS16 1 MAMR0 7 Bit symbol Read/Write After reset M0V<20:8> Enables or masks comparison of the addresses. M0V20 to M0V8 are corresponding to addresses A20 to A8. The bit of M0V14 to M0V9 is corresponding to address A14 to A9 by 1 bit. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. 1 1 1 1 M0V20 6 M0V19 5 M0V18 4 M0V17 R/W 3 M0V16 1 2 M0V15 1 1 M0V14-9 1 0 M0V8 1 MAMR1 7 Bit symbol Read/Write After reset M1V<21:8> Enables or masks comparison of the addresses. M1V21 to M1V8 are corresponding to addresses A21 to A8. The bits of M1V15 to M1V9 are corresponding to address A15 to A9 by 1 bit. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. 1 1 1 1 M1V21 6 M1V20 5 M1V19 4 M1V18 R/W 3 M1V17 1 2 M1V16 1 1 M1V15-9 1 0 M1V8 1 MAMRn (n = 2 to 3) 7 Bit symbol Read/Write After reset MnV<22:15> Enables or masks comparison of the addresses. MnV22 to MnV15 are corresponding to addresses A22 to A15. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. After a reset, MASR0 to MASR3 and MAMR0 to MAMR3 are set to "FFH". B0CSH 6 MnV21 5 MnV20 4 MnV19 R/W 3 MnV18 1 2 MnV17 1 1 MnV16 1 0 MnV15 1 92CM22-94 2007-02-16 TMP92CM22 (2) Page ROM control register (PMEMCR) The page ROM control register sets page ROM accessing. ROM page accessing is executed only in block address area 2. PMEMCR 7 Bit symbol Read/Write After reset OPGE Enable bit. 0 = No ROM page mode accessing (Default) 1 = ROM page mode accessing OPWR [1:0] Specifies the number of waits. 00 = 1 state (n-1-1-1 mode) (n 2) (Default) 01 = 2 states (n-2-2-2 mode) (n 3) 10 = 3 states (n-3-3-3 mode) (n 4) 11 = (Reserved) Note: Set the number of waits "n" to the control register (BnCSL) in each block address area. PR [1:0] ROM page size. 00 = 64 bytes 01 = 32 bytes 10 = 16 bytes (Default) 11 = 8 bytes 0 0 6 5 4 OPGE 3 OPWR1 2 OPWR0 R/W 0 1 PR1 1 0 PR0 0 92CM22-95 2007-02-16 TMP92CM22 Table 3.6.1 Control Register 7 Bit symbol Read/Write After reset B0CSH Bit symbol (0141H) Read/Write After reset MAMR0 Bit symbol (0142H) Read/Write After reset MSAR0 Bit symbol (0143H) Read/Write After reset B1CSL Bit symbol (0144H) Read/Write After reset B1CSH Bit symbol (0145H) Read/Write After reset MAMR1 Bit symbol (0146H) Read/Write After reset MSAR1 Bit symbol (0147H) Read/Write After reset B2CSL Bit symbol (0148H) Read/Write After reset B2CSH Bit symbol (0149H) Read/Write After reset MAMR2 Bit symbol (014AH) Read/Write After reset MSAR2 Bit symbol (014BH) Read/Write After reset B3CSL Bit symbol (014CH) Read/Write After reset B3CSH Bit symbol (014DH) Read/Write After reset MAMR3 Bit symbol (014EH) Read/Write After reset MSAR3 Bit symbol (014FH) Read/Write After reset BEXCSH Bit symbol (0159H) Read/Write After reset BEXCSL Bit symbol (0158H) Read/Write After reset PMEMCR Bit symbol (0166H) Read/Write After reset B0CSL (0140H) 6 B0WW2 0 - 0 (Note) M0V19 1 M0S22 1 B1WW2 0 - 0 (Note) M1V20 1 M1S22 1 B2WW2 0 5 B0WW1 W 1 - 0 (Note) M0V18 1 M0S21 1 B1WW1 W 1 - 0 (Note) M1V19 1 M1S21 1 B2WW1 W 1 - 0 (Note) M2V20 1 M2S21 1 B3WW1 W 1 - 0 (Note) M3V20 1 M3S21 1 4 B0WW0 0 B0REC W 0 M0V17 R/W 1 M0S20 R/W 1 B1WW0 0 B1REC W 0 M1V18 R/W 1 M1S20 R/W 1 B2WW0 0 B2REC W 0 M2V19 R/W 1 M2S20 R/W 1 B3WW0 0 B3REC W 0 M3V19 R/W 1 M3S20 R/W 1 3 2 B0WR2 0 B0OM0 0 M0V15 1 M0S18 1 B1WR2 0 B1OM0 0 M1V16 1 M1S18 1 B2WR2 0 1 B0WR1 W 1 B0BUS1 0 M0V14-V9 1 M0S17 1 B1WR1 W 1 B1BUS1 0 M1V15-V9 1 M1S17 1 B2WR1 W 1 B2BUS1 0 M2V16 1 M2S17 1 B3WR1 W 1 B3BUS1 0 M3V16 1 M3S17 1 BEXBUS1 W 0 BEXWR1 W 1 PR1 1 0 B0WR0 0 B0BUS0 0 M0V8 1 M0S16 1 B1WR0 0 B1BUS0 0 M1V8 1 M1S16 1 B2WR0 0 B2BUS0 0 M2V15 1 M2S16 1 B3WR0 0 B3BUS0 0 M3V15 1 M3S16 1 BEXBUS0 0 BEXWR0 0 PR0 0 B0E 0 M0V20 1 M0S23 1 B0OM1 0 M0V16 1 M0S19 1 B1E 0 M1V21 1 M1S23 1 B1OM1 0 M1V17 1 M1S19 1 B2E 1 M2V22 1 M2S23 1 B2M 0 M2V21 1 M2S22 1 B3WW2 0 - 0 (Note) M3V21 1 M3S22 1 B2OM1 0 M2V18 1 M2S19 1 B2OM0 0 M2V17 1 M2S18 1 B3WR2 0 B3OM0 0 M3V17 1 M3S18 1 BEXOM0 0 BEXWR2 0 OPWR0 R/W 0 B3E 0 M3V22 1 M3S23 1 B3OM1 0 M3V18 1 M3S19 1 BEXOM1 0 BEXWW2 0 BEXWW1 W 1 BEXWW0 0 OPGE 0 OPWR1 0 Note1: Always write "0". Note2: Read-modify-write instruction is prohibited for BnCSL, BnCSH registers (n=0 to 3, EX). 92CM22-96 2007-02-16 TMP92CM22 3.6.6 Caution If the parasitic capacitance of the read signal (Output enable signal) is greater than that of the chip select signal, it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.6.3 CLKOUT (20 MHz) Address Memory 1 chip select Memory 2 chip select RD (a) Figure 3.6.3 Read Signal Delay Read Cycle Example: When using an externally connected flash EEPROM which users JEDEC standard commands, note that the toggle bit may not be read out correctly. If the read signal in the cycle immediately preceding the access to the flash EEPROM does not go "high" in time, as shown in Figure 3.6.4 an unintended read cycle like the one shown in (b) may occur. Memory access CLKOUT (20 MHz) Address Flash EEPROM chip select Read Toggle bit (b) Toggle bit RD cycle 1 Figure 3.6.4 Flash EEPROM Toggle Bit Read Cycle When the toggle bit reverse with this unexpected read cycle, TMP92CM22 always reads same value of the toggle bit, and cannot read the toggle bit correctly. To avoid this phenomenon, the data polling control recommended. 92CM22-97 2007-02-16 TMP92CM22 (2) The cautions at the time of the functional change of a CSn . A chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control register are initialized by the reset action, and an object terminal is initialized by the port output ("1" or "0") by it. Functional change Although an object terminal is changed from a port to a chip select signal output by setting up a function control register (PnFC register), the short pulse for several ns may be outputted to the changing timing. Although it does not become especially a problem when using the usual memory, it may become a problem when using a special memory. * XX is a function register address.(When an output port is initialized by "0") A port is set as CSn . Internal Signal Internal address bus Function control signal Output port External Signal Pxx A23 to A0 n n+2 Output pulse tAD3 CSn n XX n+2 The measure by software The countermeasures in S/W for avoiding this phenomenon are explained. Since CS signal decodes the address of the access area and is generated, an unnecessary pulse is outputted by access to the object CS area immediately after setting it as a CSn function. Then, if internal area is accessed also immediately after setting a port as CS function, an unnecessary pulse will not output. 1. Prohibition of use of an NMI function 2. The ban on interruption under functional change (DI command) 3. A dummy command is added in order to carry out continuous internal access. 4. (Access to a functional change register is corresponded by 16-bit command. (LDW command)) A port is set as CSn . Internal Internal address bus Function control signal Output port External signal Pxx A23 to A0 n n+2 CSn Dummy access n+2 signal XX XX+1 92CM22-98 2007-02-16 TMP92CM22 3.7 8-Bit Timers (TMRA) The TMP92CM22 features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. * 8-bit interval timer mode * * * 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) Figure 3.7.1 and Figure 3.7.2 show block diagrams for TMRA01 and TMRA23. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five controls SFR (Special-function registers). Each of the two modules (TMRA01 and TMRA23) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter are as follows. 3.7.1 Block diagrams 3.7.2 Operation of Each Circuit 3.7.3 SFRs 3.7.4 Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM (Pulse width modulation) output mode (5) Mode settings Table 3.7.1 Registers and Pins for Each Module Module Specification Input pin for external clock External pin Output pin for timer flip-flop Timer RUN register Timer register SFR (Address) Timer mode register Timer flip-flop control register Timer A01 TA0IN (Shared with PC0) TA1OUT (Shared with PC1) TA01RUN (1100H) TA0REG (1102H) TA1REG (1103H) TA01MOD (1104H) TA1FFCR (1105H) Timer A23 None TA3OUT (Shared with PC5) TA23RUN (1108H) TA2REG (110AH) TA3REG (110BH) TA23MOD (110CH) TA3FFCR (110DH) 92CM22-99 2007-02-16 3.7.1 Prescaler 16 32 64 128 256 512 T16 Timer flip-flop TA1FF TA01RUN overflow n Prescaler clock: T0 TA01RUN 2 4 8 Run/clear T1 T4 Block Diagrams Timer flip-flop output: TA1OUT TA01RUN Selector T1 T16 T256 TA01MOD External input clock: TA0IN T1 T4 T16 Figure 3.7.1 TMRA01 Block Diagram TA01MOD 92CM22-100 8-bit comparator (CP0) TA01MOD TA01MOD Match detect 8-bit timer register TA1REG TA01RUN TMP92CM22 2007-02-16 Internal data bus TMRA0 match output: TA0TRG TMRA1 interrupt output: INTTA1 Prescaler 4 T4 T16 T256 8 16 32 64 128 256 512 Run/clear TA23RUN n Prescaler clock: T0 2 T1 Timer flip-flop output: TA3OUT TA23RUN TA3FFCR T1 T4 T16 Figure 3.7.2 TMRA23 Block Diagram 92CM22-101 8-bit comparator (CP2) Match detect TA2TRG TA23MOD TA23MOD 8-bit comparator register (CP3) Match detect 8-bit timer register TA3REG TA23RUN TMP92CM22 2007-02-16 Internal data bus TMRA2 match output: TA2TRG TMRA3 interrupt outptu: INTTA3 TMP92CM22 3.7.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The prescaler's operation can be controlled using TA01RUN Table 3.7.2 Prescaler Output Clock Resolution Clock gear selection SYSCR1 - T1(1/2) fc/16 fc/32 fc/64 fc/128 fc/256 Timer counter input clock TMRA prescaler TAxMOD fc/64 fc/128 fc/256 fc/512 fc/1024 T16(1/32) T256(1/512) fc/256 fc/512 fc/1024 fc/2048 fc/4096 fc/4096 fc/8192 fc/16384 fc/32768 fc/65536 (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks T1, T4, or T16. The clock setting is specified by the value set in TA01MOD 92CM22-102 2007-02-16 TMP92CM22 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes Active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN Timer register A0 (TA0REG) B Shift trigger Register buffer 0 Selector S A Write to TA0REG Match detecting PPG cycle n PWM 2 overflow Write Internal data bus TA01RUN Figure 3.7.3 Timer Register A0 (TA0REG) Note: The same memory address is allocated to the timer register and the register buffer. When The address of each timer register is as follows. TA0REG: 001102H TA1REG: 001103H TA2REG: 00110AH TA3REG: 00110BH All these registers are write-only and cannot be read. 92CM22-103 2007-02-16 TMP92CM22 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained below. If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up-counter value, the timer flip-flop may output an unexpected value. For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (fSYS x 6) before the next overflow occurs by using an overflow interrupt. When using PPG mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt. Example when using PWM mode Match between TA0REG and up-counter 2 overflow interrupt (INTTA0) TA1OUT tPWM (PWM cycle) n Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt 92CM22-104 2007-02-16 TMP92CM22 3.7.3 SFRs TMRA01 Run Register 7 TA01RUN Bit symbol (1100H) Read/Write After reset Function TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 0 IDLE2 0: Stop 1: Operate 0 TMRA01 prescaler 6 5 4 3 I2TA01 2 TA01PRUN R/W 1 TA1RUN 0 UP counter (UC1) 0 TA0RUN 0 UP counter (UC0) 0: Stop and clear 1: Run (Count up) TA0REG double buffer control 0 1 Disable Enable Count operation 0 1 Stop and clear Count Note: The values of bits 4 to 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 TA23RUN Bit symbol (1108H) Read/Write After reset Function TA2RDE R/W 0 Double buffer 0: Disable 1: Enable 0 IDLE2 0: Stop 1: Operate 0 TMRA23 prescaler 6 5 4 3 I2TA23 2 TA23PRUN R/W 1 TA3RUN 0 UP counter (UC3) 0 TA2RUN 0 UP counter (UC2) 0: Stop and clear 1: Run (Count up) TA2REG double buffer control 0 1 Disable Enable Count operation 0 1 Stop and clear Count Note: The values of bits 4 to 6 of TA23RUN are undefined when read. Figure 3.7.4 Register for TMRA 92CM22-105 2007-02-16 TMP92CM22 TMRA01 Mode Register 7 TA01MOD Bit symbol (1104H) Read/Write After reset Function TA01M1 0 6 TA01M0 0 5 PWM01 0 PWM cycle 00: Reserved 6 01: 2 7 10: 2 8 11: 2 4 PWM00 0 R/W 3 TA1CLK1 0 2 TA1CLK0 0 1 TA0CLK1 0 0 TA0CLK0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA1 source clock 00: TA0TRG 01: T1 10: T16 11: T256 TMRA0 source clock 00: TA0IN pin input (Note) 01: T1 10: T4 11: T16 TMRA0 input clock 00 01 10 11 TA0IN (External input) T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA1 input clock TA01MOD Matching output for TMRA0 TA01MOD Overflow output for TMRA0 T1 T16 T256 (16-bit timer mode) Select cycle in PWM mode 00 01 10 11 Reserved 2 x Source clock 6 7 2 x Source clock 2 x Source clock 8 Select operation mode for TMR01 00 01 10 11 8-bit timers x 2ch 16-bit timer 8-bit PPG 8-bit PWM (TMRA0), 8-bit timer (TMRA1) Note: When set TA0IN pin, set TA01MOD after set port C. Figure 3.7.5 Register for TMRA01 92CM22-106 2007-02-16 TMP92CM22 TMRA23 Mode Register 7 TA23MOD (110CH) Bit symbol Read/Write After reset Function 0 0 0 PWM cycle 00: Reserved 6 01: 2 7 10: 2 8 11: 2 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TA23M1 6 TA23M0 5 PWM21 4 PWM20 R/W 3 TA3CLK1 0 2 TA3CLK0 0 1 TA2CLK1 0 0 TA2CLK0 0 TMRA3 source clock 00: TA2TRG 01: T1 10: T16 11: T256 TMRA2 source clock 00: Reserved 01: T1 10: T4 11: T16 TMRA2 input clock 00 01 10 11 Don't set T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA3 input clock TA23MOD Matching output for TMRA2 Overflow output for TMRA2 T1 T16 T256 (16-bit timer mode) Select cycle in PWM mode 00 01 10 11 Reserved 2 x Source clock 6 7 2 x Source clock 2 x Source clock 8 Select operation mode for TMRA23 00 01 10 11 8-bit timer x 2ch 16-bit timer 8-bit PPG 8-bit PWM (TMRA2), 8-bit timer (TMRA3) Figure 3.7.6 Register for TMRA23 92CM22-107 2007-02-16 TMP92CM22 TMRA1 Flip Flop Control Register 7 TA1FFCR (1105H) Bit symbol Read/Write After reset Read-modify Function -write instruction is prohibited. 1 1 00: Invert TA1FF 01: Set TA1FF to "1" 10: Clear TA1FF to "0" 11: Don't care 6 5 4 3 TA1FFC1 2 TA1FFC0 R/W 1 TA1FFCIE 0 TA1FF control for inversion 0: Disable 1: Enable 0 TA1FFCIS 0 TA1FF Inversion signal select 0: TMRA0 1: TMRA1 Inversion signal for timer flip-flop 1 (TA1FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA0 Inversion by TMRA1 TA1FF control for inversion 0 1 Disable inversion Enable inversion TFF1 control 00 Note: The values of bits 4 to 7 of TA1FFCR are undefined when read. 01 10 11 Invert TA1FF Set TA1FF to "1" Clear TA1FF to "0" Don't care Figure 3.7.7 Register for TMRA 92CM22-108 2007-02-16 TMP92CM22 TMRA3 Flip-Flop Control Register 7 TA3FFCR (110DH) Bit symbol Read/Write After reset Read-modify -write instruction is prohibited. Function 1 1 00: Invert TA3FF 01: Set TA3FF to "1" 10: Clear TA3FF to "0" 11: Don't care 6 5 4 3 TA3FFC1 2 TA3FFC0 R/W 1 TA3FFCIE 0 TA3FF control for inversion 0: Disable 1: Enable 0 TA3FFCIS 0 TA3FF inversion select 0: TMRA2 1: TMRA3 Inverse signal for timer flip-flop 3 (TA3FF) (Don't care except in 8-bit timer mode) 0 1 Invert TMRA2 Invert TMRA3 TA3FF control for inversion 0 1 Disable inversion Enable inversion TA3FF control 00 Invert TA3FF Note: The values of bits 4 to 7 of TA3FFCR are undefined when read. 01 Set TA3FF to "1" 10 Clear TA3FF to "0" 11 Don't care Figure 3.7.8 Register for TMRA 92CM22-109 2007-02-16 TMP92CM22 Timer Register (TA0REG to TA3REG) Symbol TA0REG Address 1102H 7 6 5 4 - W Undefined - 3 2 1 0 TA1REG 1103H W Undefined - TA2REG 110AH W Undefined - TA3REG 110BH W Undefined Note: Read-modify-write instruction is prohibited for above registers. Figure 3.7.9 Register for TMRA 92CM22-110 2007-02-16 TMP92CM22 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. When set function and count data, TMRA0 and TMRA1 should be stopped. 1. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 40 s at fC = 40 MHz, set each register as follows: MSB 7 TA01RUN TA01MOD TA1REG INTETA01 TA01RUN X : Don't care, - 0 0 X - 6 X 0 1 1 X 5 X X 1 0 X 4 X X 0 1 X 3 - 0 0 - - 2 - 1 1 - 1 LSB 1 0 - 0 - 1 0 - - 0 - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (=(16/fc)s at fC = 40MHz) as the input clock. Set 40 s / T1 = 100 = 64H to TAREG. Enable INTTA1 and set it to Level 5. Start TMRA1 counting. - : No change Select the input clock refers to Table 3.7.3. Table 3.7.3 Selecting Interrupt Interval and the Input Clock Using 8-Bit Timer Input clock T1 (8/fSYS) T4 (32/fSYS) T16 (128/fSYS) T256 (2048/fSYS) Interrupt Interval (at fSYS = 20 MHz) 0.4 s to 102.4 s 1.6 s to 409.6 s 6.4 s to 1.638 ms 102.4 s to 26.21 ms Resolution 0.4 s 1.6 s 6.4 s 102.4 s Note: The input clocks for TMRA0 and TMRA1 differ as follows: TMRA0: Uses TMRA0 input (TA0IN) and can be selected from T1, T4, or T16. TMRA1: Matches output of TMRA0 (TA0TRG) and can be selected from T1, T16, T256. 92CM22-111 2007-02-16 TMP92CM22 2. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4 s square wave pulse from the TA1OUT pin at fC = 40 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. MSB 7 TA01RUN TA01MOD TA1REG TA1FFCR - 0 0 X 6 X 0 0 X 5 X X 0 X 4 X X 0 X 3 - 0 0 1 2 - 1 0 0 LSB 1 0 - 1 1 0 - - 1 1 Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (=(16/fc)s at fC = 40MHz) as the input clock. Set the timer register to 2.4 s / T1 / 2 = 3. Clear TA1FF to 0 and set it to invert on the match detect signal from TMRA1. PCCR PCFC TA01RUN X X - - - X - - X X X X - - - X X 1 1 1 1 - - - Set PC1 to function as the TA1OUT pin. Start TMRA1 counting. X : Don't care, - : No change T1 TA01RUN TA1FF TA1OUT 1.2 s at fC = 40 MHz Figure 3.7.10 Square Wave Output Timing Chart (50% duty) 92CM22-112 2007-02-16 TMP92CM22 3. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator (Match output forTMRA0) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) Match output for TMRA1 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.11 TMRA1 Count up on Signal from TMRA0 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer, in which TMRA0 and TMRA1 are cascaded together, set TA01MOD 92CM22-113 2007-02-16 TMP92CM22 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up-counter UC0 is not cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparator TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1, UC0) TMRA0 comparator match detect signal TMRA1 comparator match detect signal Interrupt INTTA0 Interrupt INTTA1 Timer output TA1OUT Inversion 0080H 0180H 0280H 0380H 0480H 0080H Figure 3.7.12 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active-low or active-high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin (Shared with PC1). tH Figure 3.7.13 8-Bit PPG Output Waveforms 92CM22-114 2007-02-16 TMP92CM22 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN TA01RUN TA1OUT TA1FFCR TA1FF TA01MOD Inversion INTTA0 Comparator Comparator INTTA1 Selector TA0REG Shift trigger TA0REG-WR TA01RUN Internal data bus Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied). Match with TA0REG and UC0 Match withTA1REG (Up counter = Q2) (Up counter = Q2) Shift into register buffer TA0REG (Value of compare) Register buffer Q1 Q2 Q2 Q3 Write TA0REG (Register buffer) Figure 3.7.15 Operation of Register Buffer 92CM22-115 2007-02-16 TMP92CM22 Example: To generate 1/4 duty 62.5 kHz pulses (at fC= 40 MHz): 16 s Calculate the value that should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 s T1 (= (16/fc)s (at fC = 40MHz); 16 s/(16/fc)s = 40 Therefore set TA1REG to 40 (28H) The duty is to be set to 1/4: t x 1/4 = 16 s x 1/4 = 4 s 4 s/(16/fc)s = 10 Therefore, set TA0REG = 10 = 0AH 7 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR PCCR PCFC TA01RUN X : Don't care, 0 1 0 0 X X X 1 6 X 0 0 0 X 5 X X 0 1 X 4 X X 0 0 X X X X 3 - X 1 1 0 2 0 X 0 0 1 X X 1 1 0 0 1 0 1 1 1 1 0 0 1 0 0 X Stop TMRA0 and TMRA1 and clear it to "0". Set the 8-bit PPG mode, and select T1 as input clock. Write 0AH. Write 28H. Set TA1FF and set inversion to enable. Writing "10" provides negative logic pulse. Set PC1 to TA1OUT pin. Start TMRA0 and TMRA1 counting. -- -- X X - - - - - 1 - : No change 92CM22-116 2007-02-16 TMP92CM22 (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as PC1). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7, or 8 as specified by TA01MOD Match with TA0REG and UC0 2 overflow (Interrupt INTTA0) n TA1OUT tPWM (PWM cycle) Figure 3.7.16 8-Bit Output Wave Form Figure 3.7.17 shows a block diagram representing this mode. TA01RUN Selector Clear TA1FF Inversion 2 overflow control n TA01MOD TA01MOD Comparator Overflow INTTA0 TA0REG Selector TA0REG-WR TA01RUN Internal data bus Figure 3.7.17 Block Diagram of 8-Bit PWM Output Mode 92CM22-117 2007-02-16 TMP92CM22 In this mode, the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q1 2 n Up counter = Q2 Shift from TA0REG (Register buffer) overflow Q1 Q2 Q2 Q3 Write to TA0REG TA0REG (Value of compare) Register buffer Figure 3.7.18 Operation of Register Buffer Example: To output the following PWM waves on the TA1OUT pin at fC = 40 MHz: 36.0 s 51.2 s To achieve a 51.2 s PWM cycle by setting T1=(16/fc)s (at fC = 40 MHz): 51.2 s/(16/fc)s = 128 = 2n Therefore n should be set to 7. Since the low-level period is 36.0 s when T1 = (16/fc)s, set the following value for TA0REG: 36.0 s/(16/fc)s = 90 = 5AH MSB 7 TA01RUN TA01MOD TA0REG TA1FFCR PCCR PCFC TA01RUN - 1 0 X X X 1 6 X 1 1 X 5 X 1 0 X 4 X 0 1 X X X X 3 2 LSB 1 0 0 1 0 X - - 1 Stop TMRA0 and clear it to 0. Select 8-bit PWM mode (cycle: 2 ) and select T1 as the input clock. 7 --- -- 0 1 1 - 0 0 X X 1 1 1 1 1 - Write 5AH. Clear TA1FF to 0; set inversion to enable. -- -- X X - - Set PC1 to TA1OUT pin. Start TMRA0 counting. X : Don't care, - : No change 92CM22-118 2007-02-16 TMP92CM22 Table 3.7.4 Relationship of PWM Cycle and 2n Counter Clock gear SYSCR1 PWM cycle TAxxMOD 4096/fc 8192/fc 16384/fc 32768/fc 65536/fc 6 2 (x128) TAxxMOD 2048/fc 4096/fc 8192/fc 16384/fc 32768/fc 7 2 (x256) TAxxMOD 4096/fc 8192/fc 16384/fc 32768/fc 65536/fc 8 T16(x32) 16384/fc 32768/fc 65536/fc 131072/fc 262144/fc T4(x8) 8192/fc 16384/fc 32768/fc 65536/fc 131072/fc T16(x32) 32768/fc 65536/fc 131072/fc 262144/fc 524288/fc T4(x8) 16384/fc 32768/fc 65536/fc 131072/fc 262144/fc T16(x32) 65536/fc 131072/fc 262144/fc 524288/fc 1048576/fc 000(x1) 001(x2) 010(x4) 011(x8) 100(x16) 0(fc) x8 1024/fc 2048/fc 4096/fc 8192/fc 16384/fc (5) Mode settings Table 3.7.5 shows the SFR settings for each mode. Table 3.7.5 Timer Mode Setting Registers Register Name 8-bit timer x 2 channels 00 - 8-bit PPG x 1 channel 10 6 - 7 8 - - 8-bit PWM x 1 channel 8-bit timer x 1 channel 11 2,2,2 (01, 10, 11) - - T1, T16, T256 (01, 10, 11) - 11 Output disable - : Don't care 92CM22-119 2007-02-16 TMP92CM22 3.8 16-Bit Timer/Event Counters (TMRB) The TMP92CM22 contains 2 channels 16-bit timer/event counter (TMRB) which have the following operation modes: * * * 16-bit interval timer mode 16-bit event counter mode 16-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) Can be used following operation modes by capture function: * Frequency measurement mode * * Pulse width measurement mode Time differential measurement mode Figure 3.8.1 to Figure 3.8.2 show block diagram of TMRB0 and TMRB1. Each timer/event counter consists of a 16-bit up counter, two 16-bit timer registers (One of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, a timer flip-flop and a control circuit. Each timer/event counter is controlled by 11-byte control register (SFR). This chapter consists of the following items: 3.8.1 Block diagram 3.8.2 Operation 3.8.3 SFRs 3.8.4 Operation in Each Mode (1) 16-bit interval timer mode (2) 16-bit event/counter mode (3) 16-bit programmable pulse generation (PPG) output mode (4) Capture function examples Table 3.8.1 Pins and SFR of TMRB Channel Spec External clock/ External pin Caputre triggr input pin Timer flip-flop output pin Timre run register Timrer mode register Timre flip-flop control register TB0OUT0 (Share with PC6) TB0RUN (1180H) TB0MOD (1182H) TB0FFCR (1183H) TB0RG0L (1188H) SFR (Address) Timer register TB0RG0H (1189H) TB0RG1L (118AH) TB0RG1H (118BH) TB0CP0L (118CH) Capture register TB0CP0H (118DH) TB0CP1L (118EH) TB0CP1H (118FH) TMRB0 None TMRB1 TB1IN0 (Share with PD0) TB1IN1 (Share with PD1) TB1OUT0 (Share with PD2) TB1OUT1 (Share with PD3) TB1RUN (1190H) TB1MOD (1192H) TB1FFCR (1193H) TB1RG0L (1198H) TB1RG0H (1199H) TB1RG1L (119AH) TB1RG1H (119BH) TB1CP0L (119CH) TB1CP0H (119DH) TB1CP1L (119EH) TB1CP1H (119FH) 92CM22-120 2007-02-16 Interrupt output 3.8.1 Internal data bus Register 0 INTTB00 Register 1 INTTB01 Internal data bus Run/ clear 8 T4 Capture register 0 TB0CP0H/L Caputure register 1 TB0CP1H/L Timer flip-flop T16 16 32 TB0RUN Prescaler clock: T0 2 4 Block Diagram T1 (from TMRA01) TA1OUT control Selector T1 T4 T16 Count clock 16-bit up counter (UC10) TB0RUN TB0MOD Timer flip-flop output Capture, external interrupt TB0FF0 TB0OUT0 TB0MOD Figure 3.8.1 Block Diagram of TMRB0 92CM22-121 TB0MOD Overflow interrupt INTTBOF0 Match detection 16-bit comparator (CP11) 16-bit timer register TB0RG1H/L TB0RUN TMP92CM22 2007-02-16 Intenal data bus Interrupt output Internal data bus Register 0 INTTB00 Register 1 INTTB01 Internal data bus Run/ clear 8 T4 Capture register 0 TB1CP0H/L Caputure register 1 TB1CP1H/L Timer flip-flop TB0FF0 Timer flip-flop control TB0FF1 T16 16 32 TB1RUN Prescaler clock: T0 2 4 External interrupt input TB1MOD T1 INT4 INT5 (from TMRA23) TA1OUT Timer flip-flop output TB1OUT0 TB1OUT1 TB1IN0 TB1IN1 Selector T1 T4 T16 Count clock 16-bit up counter (UC1) TB1RUN Capture, external interrupt control Figure 3.8.2 Block Diagram of TMRB1 92CM22-122 TB1MOD TB1MOD Overflow interrupt INTTBOF0 Match detection 16-bit comparator (CP13) 16-bit timer register TB1RG1H/L TB1RUN TMP92CM22 2007-02-16 Intenal data bus TMP92CM22 3.8.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (T0) is a divided clock (Divided by 8) from selected clock by the register SYSCR1 Clock gear selection SYSCR1 Timer counter input clock TMRB prescaler - TB0MOD fc/16 fc/32 fc/64 fc/128 fc/256 T4 (1/8) fc/64 fc/128 fc/256 fc/512 fc/1024 T16 (1/32) fc/256 fc/512 fc/1024 fc/2048 fc/4096 (2) Up counter (UC10) UC10 is a 16-bit binary counter that counts up according to input from the clock specified by TB0MOD 92CM22-123 2007-02-16 TMP92CM22 (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower timer registers TB0RG0H/L and TB0RG1H/L is always needed. For example, either using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order. The TB0RG0H/L timer register has a double-buffer structure, which is paired with register buffer 10. The value set in TB0RUN TMRB0 TB0RG0H/L Upper 8 bits (TB0RG0H) 1189H Lower 8 bits (TB0RG0L) 1188H TB0RG1H/L Upper 8 bits (TB0RG1H) 118BH Lower 8 bits (TB0RG1L) 118AH TMRB1 TB1RG0H/L Upper 8 bits (TB1RG0H) 1199H Lower 8 bits (TB1RG0L) 1198H TB1RG1H/L Upper 8 bits (TB1RG1H) 119BH Lower 8 bits (TB1RG1L) 119AH The timer registers are write-only registers and thus cannot be read. 92CM22-124 2007-02-16 TMP92CM22 (4) Capture registers (TB0CP0H/L, TB0CP1H/L, TB1CP0H/L and TB1CP1H/L) These 16-bit registers are used to latch the values in the up counters UC10. Data in the capture registers should be read both upper and lower all 16 bits. For example, using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order. The addresses of the capture registers are as follows: TMRB0 TB0CP0H/L Upper 8 bits (TB0CP0H) 118DH Lower 8 bits (TB0CP0L) 118CH TB0CP1H/L Upper 8 bits (TB0CP1H) 118FH Lower 8 bits (TB0CP1L) 118EH TMRB1 TB1CP0H/L Upper 8 bits (TB1CP0H) 119DH Lower 8 bits (TB1CP0L) 119CH TB1CP1H/L Upper 8 bits (TB1CP1H) 119FH Lower 8 bits (TB1CP1L) 119EH The capture registers are read-only registers and thus cannot be written. (5) Capture and external interrupt control This circuit controls the timing to latch the value of up counter UC10 into TB0CP0H/L, TB0CP1H/L and generating for external interrupt. Interrupt timing of capture register and selection edge of external interrupt are set by TB0MOD 92CM22-125 2007-02-16 TMP92CM22 (6) Comparators (CP10 and CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively). (7) Timer flip-flop (TB0FF0 and TB0FF1) These flip-flops (TB0FF0 and TB0FF1) are inverted by the match detect signals from the comparators and the latch signals to the capture registers. Inversion can be enabled and disabled for each element using TB0FFCR 92CM22-126 2007-02-16 TMP92CM22 3.8.3 SFRs TMRB0 Run Register 7 TB0RUN (1180H) Bit symbol Read/Write After reset Function 0 Double buffer 0: Disable 1: Enable TB0RDE R/W 0 Always write "0". 0 IDLE2 0: Stop 1: Operate 6 - 5 4 3 I2TB0 R/W 2 TB0PRUN 0 TMRB0 Prescaler 0: Stop and clear 1: Run (Count) 1 0 TB0RUN R/W 0 Up counter UC10 Count operation 0 1 Stop and clear Count Note: The values of bits 1, 4, and 5 of TB0RUN are undefined when read. TMRB1 Run Register 7 TB1RUN (1190H) Bit symbol Read/Write After reset Function 0 Double buffer 0: Disable 1: Enable TB1RDE R/W 0 Always write "0". 0 IDLE2 0: Stop 1: Operate 6 - 5 4 3 I2TB1 R/W 2 TB1PRUN 0 TMRB1 Prescaler 0: Stop and clear 1: Run (Count) 1 0 TB1RUN R/W 0 Up counter UC12 Count operation 0 1 Stop and clear Count Note: The values of bits 1, 4, and 5 of TB1RUN are undefined when read. Figure 3.8.3 Register for TMRB 92CM22-127 2007-02-16 TMP92CM22 TMRB0 Mode Register 7 TB0MOD (1182H) Read-modify -write instruction is prohibited Bit symbol Read/Write After reset Function 0 Always write "0". - R/W 0 Always write "0". 6 - 5 TB0CP0I W 1 Software capture control 4 TB0CPM1 0 Capture timing 00: Disable 01: (Reserved) 3 TB0CPM0 0 2 TB0CLE R/W 0 Up counter control 0: Clear disable 1: Clear enable 1 TB0CLK1 0 00: (Reserved) 01: T1 10: T4 11: T16 0 TB0CLK0 0 TMRB0 source clock 0: Software 10: (Reserved) capturer 11: TA1OUT TA1OUT 1: Undefined Input clock 00 01 10 11 Reserved T1 T4 T16 Clear up counter 0(UC0) 0 1 Disable Enable clearing on match with TB0RG1H/L Capture/interrupt timing Capture control 00 01 10 11 Disable (Reserved) (Reserved) Capture to TB0CP0H/L at rising edge of TA1OUT Capture to TB0CP1H/L at falling edge of TA1OUT Software capture 0 1 Capture value of up counter to TB0CP0H/L Undefined Figure 3.8.4 Register for TMRB 92CM22-128 2007-02-16 TMP92CM22 TMRB1 Mode Register 7 TB1MOD (1192H) Bit symbol Read/Write After reset Read-modify -write instruction is prohibited Function 0 0: Trigger disable 1: Trigger enable Invert when UC12 is loaded into TB1CP1H/L Invert when UC12 matches with TB1RG1H/L 6 TB1ET1 R/W 0 5 TB1CP0I W 1 Software capture control 00: 4 TB1CPM1 0 Capture timing 3 TB1CPM0 0 2 TB1CLE R/W 0 Up counter control 0: Clear disable 1 TB1CLK1 0 0 TB1CLK0 0 TB1CT1 TB1FF1 Inversion trigger TMRB1 source clock 00: TB1IN0 pin input 01: T1 10: T4 11: T16 Disable INT4 is rising edge TB1N0 TB1IN1 INT4 is falling edge 0: Software 01: capture 1: Undefined 10: 11: 1: Clear TB1IN0 TB1IN0 enable INT4 is falling edge TA1TRG TA1TRG INT4 is rising edge Input clock 00 TB1IN0 pin input 01 T1 10 T4 11 T16 Clear up counter (UC12) 0 1 Clear disable Clear by matching with TB1RG1H/L Capture/interrupt timing Capture control 00 Capture disable 01 Capture to TB1CP0H/L at rising edge of TB1IN0 Capture to TB1CP1H/L at rising edge of TB1IN1 INT4 control Generate INT4 by TB1IN0 rising Generate INT4 by TB1IN0 falling 10 Capture to TB1CP0H/L at rising edge of TB1IN0 Capture to TB1CP1H/L at falling edge of TB1IN1 11 Capture to TB1CP0H/L at rising edge of TA1OUT Generate INT4 Capture to TB1CP1H/L at falling edge of TA1OUT by TB1IN0 rising Software capture 0 1 Capture value of up counter to TB1CP0H/L Undefined Figure 3.8.5 Register for TMRB 92CM22-129 2007-02-16 TMP92CM22 TMRB0 Flip-flop Control Register 7 TB0FFCR (1183H) Bit symbol Read/Write After reset Read-modify -write instruction is prohibited Function 1 Always write "11". - W 1 0 0: Trigger disable 1: Trigger enable Invert when the UC10 value is loaded into TB0CP1H/L Invert when the UC10 value is loaded into TB0CP0H/L Invert when the UC10 matches with TB0RG1H/L 6 - 5 TB0C1T1 4 TB0C0T1 0 R/W 3 TB0E1T1 0 2 TB0E0T1 0 1 TB0FFC1 W* 1 TB0FF0 control 00: Invert 01: Set 0 TB0FFC0 1 TB0FF0 inversion trigger Invert when 10: Clear the UC10 11: Don't care match with * Always read as "11". TB0RG0H/L Timer flip-flop TB0 (TB0FF0) control 00 Invert 01 10 11 Set to "1". Set to "0". Don't care. Inverted when the UC10 value matches the value in TB0RG0H/L 0 1 Disable inversion Enable inversion Inverted when the UC10 value matches the value in TB0RG1H/L 0 1 Disable inversion Enable inversion Inverted when the UC10 value is loaded into TB0CP0H/L 0 1 Disable inversion Enable inversion Inverted when the UC10 value is loaded into TB0CP1H/L 0 1 Disable inversion Enable inversion Figure 3.8.6 Register for TMRB 92CM22-130 2007-02-16 TMP92CM22 TMRB1 Flip-flop Control Register 7 TB1FFCR (1193H) Bit symbol Read/Write After reset Read-modify Function -write instruction is prohibited 1 TB1FF1 control 00: Invert 01: Set 10: Clear 11: Don't care * Always read as "11". TB1FF1C1 W* 1 0 0: Trigger disable 1: Trigger enable Invert when the UC12 value is loaded into TB1CP1H/L. Invert when the UC12 value is loaded into TB1CP0H/L. Invert when the UC12 matches with TB1RG1H/L. Invert when the UC12 match with TB1RG0H/L. 6 TB1FF1C0 5 TB1C1T1 4 TB1C0T1 0 R/W 3 TB1E1T1 0 2 TB1E0T1 0 1 TB1FFC1 W* 1 TB1FF0 control 00: Invert 01: Set 10: Clear 11: Don't care 0 TB1FFC0 1 TB1FF0 inversion trigger * Always read as "11". Timer flip-flop TB1 (TB1FF0) control 00 01 10 11 Invert Set to "1". Set to "0". Don't care Inverted when the UC12 value matches the value in TB1RG0H/L 0 1 Disable inversion Enable inversion Inverted when the UC12 value matches the value in TB1RG1H/L 0 1 Disable inversion Enable inversion Inverted when the UC12 value is loaded into TB1CP0H/L 0 1 Disable inversion Enable inversion I Inverted when the UC12 value is loaded into TB1CP1H/L 0 1 Disable inversion Enable inversion TB1FF1 control 00 01 10 11 Invert value of TB1FF1 Set TB1FF1 to "1". Set TB1FF1 to "0". Don't care Figure 3.8.7 Register for TMRB 92CM22-131 2007-02-16 TMP92CM22 TMRB0 register 5 4 - W Undefined - W Undefined - W Undefined - W Undefined - W Undefined - W Undefined - W Undefined - W Undefined 7 TB0RG0L (1188H) bit Symbol Read/Write After reset TB0RG0H (1189H) bit Symbol Read/Write After reset TB0RG1L (118AH) bit Symbol Read/Write After reset TB0RG1H (118BH) bit Symbol Read/Write After reset TB0CP0L (118CH) bit Symbol Read/Write After reset TB0CP0H bit Symbol (118DH) Read/Write After reset TB0CP1L (118EH) bit Symbol Read/Write After reset TB0CP1H bit Symbol (118FH) Read/Write After reset 6 3 2 1 0 TMRB1 register 7 TB1RG0L (1198H) bit Symbol Read/Write After reset TB1RG0H (1199H) bit Symbol Read/Write After reset TB1RG1L (119AH) bit Symbol Read/Write After reset TB1RG1H (119BH) bit Symbol Read/Write After reset TB1CP0L (119CH) bit Symbol Read/Write After reset TB1CP0H bit Symbol (119DH) Read/Write After reset TB1CP1L (119EH) bit Symbol Read/Write After reset TB1CP1H bit Symbol (119FH) Read/Write After reset 6 5 4 - W Undefined - W Undefined - W Undefined - W Undefined - W Undefined - W Undefined - W Undefined - W Undefined 3 2 1 0 Note: All registers are prohibited to execute read-modify-write instruction. Figure 3.8.8 Register for TMRB 92CM22-132 2007-02-16 TMP92CM22 3.8.4 Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals in this example, the interval time is set the timer register TB0RG1H/L to generate the interrupt INTTB01. 76543210 TB0RUN INTETB0 TB0FFCR TB0MOD TB0RG1 TB0RUN 00XX-0X0 X100X000 11000011 001001* * * * * * * * * * * * * * * * * * (** = 01, 10, 11) Stop TMRB0. Enable INTTB01 and set interrupt level 4. Disable INTTB00. Disable the trigger. Set input clock to prescaler clock, and set capture function to disable. Set the interval time. (16 bits) Start TMRB0. 00XX-1X1 X : Don't care, - : No change (2) 16-bit event counter mode In 16-bit timer mode as described in above, the timer can be used as an event counter by selecting the external clock (TB1IN0 pin input) as the input clock. Up counter counting up by rising edge of TB1IN0 pin input. And execution software capture and reading capture value enable reading count value. 76543210 TB1RUN PDCR PDFC INTETB1 TB1FFCR TB1MOD TB1RG1 TB1RUN 00XX-0X0 XXXX---0 XXXX---1 X100X000 11000011 00100100 * * * * * * * * * * * * * * * * Set INTTB11 to enable (Interrupt level4). Set INTTB00 to disable. Set trigger to disable. Set input clock to TB1IN0 pin input. Set number of count. (16 bits) Start TMRB1. Stop TMRB1. Set PD0 to TB1IN0 input mode. 00XX-1X1 X: Don't care, -: No change Note: When used as an event counter, set the prescaler to "RUN" (TB1RUN 92CM22-133 2007-02-16 TMP92CM22 (3) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low active or high active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be enabled by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L and to be output to TB0OUT0. In this mode, the following conditions must be satisfied. (Set value of TB0RG0H/L) < (Set value of TB0RG1H/L) Match with TB0RG0H/L (INTTB00 interrupt ) Match with TB0RG1H/L (INTTB01 interrupt) TB0OUT0 pin Figure 3.8.9 Programmable Pulse Generation (PPG) Output Waveforms When the TB0RG0H/L double buffer is enabled in this mode, the value of register buffer 10 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature makes easy the handling of low-duty waves. Match with TB0RG0H/L Up counter = Q1 Match with TB0RG1H/L Shift in to TB0RG1H/L TB0RG0H/L (Compare value) Register buffer 10 Q1 Q2 Q2 Q3 Write TB0RG0H/L Up counter = Q2 Figure 3.8.10 Operation of Register Buffer 92CM22-134 2007-02-16 TMP92CM22 The following block diagram illustrates this mode. TB0RUN Matching 16-bit comparator 16-bit comparator Selector TB0RG0H/L TB0RG0-WR Register buffer 10 TB0RUN Figure 3.8.11 Block Diagram of 16-Bit PPG Mode The following example shows how to set 16-bit PPG output mode: 76543210 TB0RUN 00XX-0X0 TB0RG0H/L * * * * * * * * * TB0RG1H/L * * TB0RUN * * * * * * * * * * * * * * * * * * * * * Disable the TB0RG0H/L double buffer and stop TMRB0. Set the duty ratio. (16 bits) Set the frequency. (16 bits) Enable the TB0RG0 double buffer. (The duty and frequency are changed on an INTTB01 interrupt.) Set the mode to invert TB0FF0 at the match with TB0RG0H/L/TB0RG1H?L. Clear TB0FF0 to 0. Set input clock to prescaler output clock and disable the capture function. 10XX-0X0 TB0FFCR TB0MOD XX001110 001001* * (** = 01, 10, 11) PCCR PCFC TB0RUN X1-X-X-- X1-X-X-- 10XX-1X1 Set PC6 to function as TB0OUT0. Start TMRB0. X : Don't care, - : No change 92CM22-135 2007-02-16 TMP92CM22 (4) Capture function examples Used capture function, they can be applicable in many ways, for example: 1. 2. 3. 4. 1. One-shot pulse output from external trigger pulse Frequency measurement Pulse width measurement Measurement of difference time One-shot pulse output from external trigger pulse Set the up counter UC12 in free-running mode with the internal input clock, input the external trigger pulse from TB1IN0 pin, and load the value of up counter into capture register TB1CP0H/L at the rise edge of external trigger pulse. When the interrupt INT4 is generated at the rise edge of external trigger pulse, set the TB1CP0H/L value (c) plus a delay time (d) to TB1RG0H/L (= c + d), and set the above set value (c + d) plus a one-shot width (p) to TB1RG1H/L (= c + d + p). And, set "11" to timer flip-flop control register TB1FFCR Set the counter in free-running mode. Count clock (Prescaler output clock) TB1IN0 pin input (External trigger pulse) Match with TB1RG0H/L c c+d c+d+p Load into capture register 1 (TB1CP0H/L) and generate INT4. Inversion enable Inversion Set it to disables that enable inversion caused by loading into TB1CP1H/L. Delay time (d) Pulse width (p) Generate INTTB11. Match with TB1RG1H/L Timer ouput pin TB1OUT0 Figure 3.8.12 One-shot Pulse Output (with delay) 92CM22-136 2007-02-16 TMP92CM22 Example: To output a 2 [ms] one-shot pulse with a 3 [ms] delay to the external trigger pulse via the TB1IN0 pin. * Clock state : Setting in Main Set free running. Count using T1. TB1MOD TB1FFCR XX101001 Load into TB1CP0H/L by rising edge of TB1IN0 pin input. XX000010 Clear TB1FF0 to 0. Disable inversion of TB1FF0. PDCR PDFC INTE45 INTETB1 TB1RUN XXXX-1-- XXXX-1XX X---X100 X000X000 -0XX-1X1 Set PD2 to function as the TB1OUT0 pin. Clock gear 1/1 (fc) Enable INT4. Disable INTTB10 and INTTB11. Start TMRB0. Setting in INT4 TB1RG0H/L TB1CP0H/L + 3 ms/T1 TB1RG1H/L TB1RG0H/L + 2 ms/T1 TB1FFCR XX--11-- Enable inversion of TB1FF0 when match with TB1RG0G/L or TB1RG1G/L. INTETB1 X100X--- Set INTTB11 to enable. Setting in INTTB11 TB1FFCR XX--00-- Disable inversion of TB1FF0 when match with TB1RG0H/L or TB1RG1H/L. INTETB1 X000X--- Disable INTTB11. X : Don't care, - : No change When delay time is unnecessary, invert timer flip-flop TB1FF0 when up counter value is loaded into capture register (TB1CP0H/L), and set the TB1CP0H/L value (c) plus the one-shot pulse width (p) to TB0RG1H/L when the interrupt INT4 occurs. The TB1FF0 inversion should be enable when the up counter (UC12) value matches TB1RG1H/L, and disabled when generating the interrupt INTTB11. 92CM22-137 2007-02-16 TMP92CM22 Count clock (Prescaler output clock) c TB1IN0 input (External trigger pulse) Match with TB1RG1H/L Inversion enable Timer output TB1OUT0 pin Pulse width (p) Set it to enable that inversion caused by loading into TB1CP0H/L. c+p Load into capture register TB1CP0H/L generate INT4. Generate INTTB11. Load into capture register 1 TB1CP1H/L. Set it to disable that inversion caused by loading into TB1CP1H/L. Figure 3.8.13 One-shot Pulse Output (without delay) 2. Frequency measurement The frequency of the external clock can be measured in this mode. Frequency is measured by the 8-bit timers TMRA23 and the 16-bit timer/event counter. TMRA23 is used to setting of measurement time by inversion TA3FF. Counter clock in TMRB0 select TB1IN0 pin input, and count by external clock input. Set to TB1MOD Count clock (TB1IN0 pin input ) TA3FF Load into TB1CP0H/L Load into TB1CP1H/L INTTA2/INTTA3 C1 C2 C1 C2 C1 C2 Figure 3.8.14 Frequency Measurement For example, if the value for the level 1 width of TA3FF of the 8-bit timer is set to 0.5 s and the difference between the values in TB1CP0H/L and TB1CP1H/L is 100, the frequency is 100 / 0.5 s = 200 Hz. 92CM22-138 2007-02-16 TMP92CM22 3. Pulse width measurement This mode allows measuring the high level width of an external pulse. While keeping the 16-bit timer/event counter counting (Free running) with the prescaler output clock input, external pulse is input through the TB1IN0 pin. Then the capture function is used to load the UC12 values into TB1CP0H/L and TB1CP1H/L at the rising edge and falling edge of the external trigger pulse respectively. The interrupt INT4 occurs at the falling edge of TB1IN0. The pulse width is obtained from the difference between the values of TB1CP0H/L and TB1CP1H/L and the internal clock cycle. For example, if the prescaler output clock is 0.8 s and the difference between TB1CP0H/L and TB1CP1H/L is 100, the pulse width will be 100 x 0.8 s = 80 s. Additionally, the pulse width that is over the UC12 maximum count time specified by the clock source can be measured by changing software. Count clock (Prescaler output clock) C1 TB1IN0 pin input (External pulse) Load into TB0CP0H/L Load into TB0CP1H/L INT4 C1 C2 C1 C2 C2 Figure 3.8.15 Pulse Width Measurement Note: Pulse Width measure by setting "10" to TB1MOD The width of low level can be measured from the difference between the first C2 and the second C1 at the second INT4 interrupt. 92CM22-139 2007-02-16 TMP92CM22 4. Measurement of difference time This mode is used to measure the difference in time between the rising edges of external pulses input through TB1IN0 and TB1IN1. Keep the 16-bit timer/event counter (TMRB1) counting (Free running) with the prescaler output clock, and load the UC12 value into TB1CP0H/L at the rising edge of the input pulse to TB1IN0. Then the interrupt INT4 is generated. Similarly, the UC012 value is loaded into TB1CP1H/L at the rising edge of the input pulse to TB1IN1, generating the interrupt INT5. The time difference between these pulses can be obtained by multiplying the value subtracted TB1CP0H/L from TB1CP1H/L and the internal clock cycle together at which loading the UC12 value into TB1CP0H/L and TB1CP1H/L has been done. Count clock (Prescaler output clock) C1 TB1IN0 pin input TB1IN1 pin input Load into TB1CP0H/L Load intoTB1CP1H/L INT4 INT5 Difference time C2 Figure 3.8.16 Measurement of Difference Time 92CM22-140 2007-02-16 TMP92CM22 3.9 Serial Channels (SIO) The TMP92CM22 includes 2 serial I/O channels. Each channel is called SIO0 and SIO1. For both channels either UART Mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. * I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. Mode 1: 7-bit data * UART mode Mode 2: 8-bit data Mode 3: 9-bit data In mode 1 and mode 2 a parity bit can be added. Mode 3 has a wakeup function for making the master controller start slave controllers via a serial link (Multi-controller system). Figure 3.9.2 and Figure 3.9.3 are block diagrams for each channel. Each channel is structured in prescaler, serial clock generation circuit, receiving buffer and control circuit, and transfer buffer and control circuit. Serial channels 0 and 1 can be used independently. Both channels operate in the same function except for the following points; hence only the operation of channel 0 is explained below. Table 3.9.1 Differences between Channels 0 to 1 Channel 0 Pin name TXD0 (PF0) RXD0 (PF1) CTS0 /SCLK0 (PF2) Channel 1 TXD1 (PF3) RXD1 (PF4) CTS1 /SCLK1 (PF5) IrDA mode Yes No This chapter contains the following sections: 3.9.1 Block Diagram 3.9.2 Operation of Each Circuit 3.9.3 SFRs 3.9.4 Operation in Each Mode 3.9.5 Support for IrDA Mode 92CM22-141 2007-02-16 TMP92CM22 * Mode 0 (I/O interface mode) Bit0 1 2 3 4 5 6 7 Transfer direction * Mode 1 (7-bit UART mode) No parity Parity Start Start Bit0 Bit0 1 1 2 2 3 3 4 4 5 5 6 6 Stop Parity Stop * Mode 2 (8-bit UART mode) No parity Parity Start Start Bit0 Bit0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Stop Parity Stop * Mode 3 (9-bit UART mode) Start Wakeup Start Bit0 Bit0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 Bit8 Stop Stop If bit8=1, denoted address (Select code). If bit8=0, denoted data. Figure 3.9.1 Data Format 92CM22-142 2007-02-16 TMP92CM22 3.9.1 T0 Block Diagram Prescaler 2 4 8 16 32 64 T2 T8 T32 Serial clock generation circuit BR0CR |